Hypervisor extension

LICENCE

@@ -24,6 +24,7 @@ Copyright (c) 2017-2024
    Jan Henrik Weinstock
    Jessica Clarke
    Jon French
+   KULeuven, for contributions by Lowie Deferme
    Martin Berger
    Michael Sammler
    Microsoft, for contributions by Robert Norton-Wright and Nathaniel Wesley Filardo

Makefile

@@ -47,6 +47,8 @@ SAIL_DEFAULT_INST += riscv_insts_zbkx.sail
 
 SAIL_DEFAULT_INST += riscv_insts_zicond.sail
 
+SAIL_DEFAULT_INST += riscv_insts_hext.sail
+
 SAIL_DEFAULT_INST += riscv_insts_vext_utils.sail
 SAIL_DEFAULT_INST += riscv_insts_vext_fp_utils.sail
 SAIL_DEFAULT_INST += riscv_insts_vext_vset.sail
@@ -74,6 +76,9 @@ SAIL_SYS_SRCS =  riscv_csr_begin.sail       # Start of CSR scattered definitions
 SAIL_SYS_SRCS += riscv_vext_control.sail    # helpers for the 'V' extension
 SAIL_SYS_SRCS += riscv_sys_exceptions.sail  # default basic helpers for exception handling
 SAIL_SYS_SRCS += riscv_sync_exception.sail  # define the exception structure used in the model
+SAIL_SYS_SRCS += riscv_zicsr_control.sail   # helpers for the Zicsr extension
+SAIL_SYS_SRCS += riscv_hext_control.sail    # helpers for the hypervisor extension
+SAIL_SYS_SRCS += riscv_csr_hext.sail        # scattered definition for hypervisor extension CSRs
 SAIL_SYS_SRCS += riscv_softfloat_interface.sail riscv_fdext_regs.sail riscv_fdext_control.sail
 SAIL_SYS_SRCS += riscv_sys_control.sail     # general exception handling
 
@@ -97,15 +102,16 @@ SAIL_VM_SRCS += riscv_vmem.sail
 PRELUDE = prelude.sail $(SAIL_XLEN) $(SAIL_FLEN) $(SAIL_VLEN) prelude_mem_metadata.sail prelude_mem.sail
 
 SAIL_REGS_SRCS = riscv_reg_type.sail riscv_freg_type.sail riscv_regs.sail riscv_pc_access.sail riscv_sys_regs.sail
+SAIL_REGS_SRCS += riscv_hext_regs.sail
 SAIL_REGS_SRCS += riscv_pmp_regs.sail riscv_pmp_control.sail
 SAIL_REGS_SRCS += riscv_ext_regs.sail $(SAIL_CHECK_SRCS)
 SAIL_REGS_SRCS += riscv_vreg_type.sail riscv_vext_regs.sail
 
 SAIL_ARCH_SRCS = $(PRELUDE)
 SAIL_ARCH_SRCS += riscv_types_common.sail riscv_types_ext.sail riscv_types.sail
-SAIL_ARCH_SRCS += riscv_vmem_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail
+SAIL_ARCH_SRCS += riscv_types_hext.sail riscv_vmem_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail
 SAIL_ARCH_SRCS += riscv_mem.sail $(SAIL_VM_SRCS)
-SAIL_ARCH_RVFI_SRCS = $(PRELUDE) rvfi_dii.sail riscv_types_common.sail riscv_types_ext.sail riscv_types.sail riscv_vmem_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail riscv_mem.sail $(SAIL_VM_SRCS) riscv_types_kext.sail
+SAIL_ARCH_RVFI_SRCS = $(PRELUDE) rvfi_dii.sail riscv_types_common.sail riscv_types_ext.sail riscv_types.sail riscv_vmem_types.sail riscv_types_hext.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail riscv_mem.sail $(SAIL_VM_SRCS) riscv_types_kext.sail
 SAIL_ARCH_SRCS += riscv_types_kext.sail    # Shared/common code for the cryptography extension.
 
 SAIL_STEP_SRCS = riscv_step_common.sail riscv_step_ext.sail riscv_decode_ext.sail riscv_fetch.sail riscv_step.sail

c_emulator/riscv_platform.c

@@ -72,6 +72,11 @@ bool sys_enable_zicboz(unit u)
   return rv_enable_zicboz;
 }
 
+bool sys_enable_hext(unit u)
+{
+  return rv_enable_hext;
+}
+
 uint64_t sys_pmp_count(unit u)
 {
   return rv_pmp_count;

c_emulator/riscv_platform.h

@@ -13,6 +13,7 @@ bool sys_enable_vext(unit);
 bool sys_enable_bext(unit);
 bool sys_enable_zicbom(unit);
 bool sys_enable_zicboz(unit);
+bool sys_enable_hext(unit);
 
 uint64_t sys_pmp_count(unit);
 uint64_t sys_pmp_grain(unit);

c_emulator/riscv_platform_impl.c

@@ -20,6 +20,7 @@ bool rv_enable_vext = true;
 bool rv_enable_bext = false;
 bool rv_enable_zicbom = false;
 bool rv_enable_zicboz = false;
+bool rv_enable_hext = false;
 
 bool rv_enable_dirty_update = false;
 bool rv_enable_misaligned = false;

c_emulator/riscv_platform_impl.h

@@ -24,6 +24,7 @@ extern bool rv_enable_vext;
 extern bool rv_enable_bext;
 extern bool rv_enable_zicbom;
 extern bool rv_enable_zicboz;
+extern bool rv_enable_hext;
 extern bool rv_enable_writable_misa;
 extern bool rv_enable_dirty_update;
 extern bool rv_enable_misaligned;

c_emulator/riscv_sim.c

@@ -134,6 +134,7 @@ static struct option options[] = {
     {"pmp-count",                   required_argument, 0, OPT_PMP_COUNT           },
     {"pmp-grain",                   required_argument, 0, OPT_PMP_GRAIN           },
     {"enable-next",                 no_argument,       0, 'N'                     },
+    {"enable-hext",                 no_argument,       0, 'H'                     },
     {"ram-size",                    required_argument, 0, 'z'                     },
     {"disable-compressed",          no_argument,       0, 'C'                     },
     {"disable-writable-misa",       no_argument,       0, 'I'                     },
@@ -272,6 +273,7 @@ static int process_args(int argc, char **argv)
     c = getopt_long(argc, argv,
                     "a"
                     "B"
+                    "H"
                     "d"
                     "m"
                     "P"
@@ -310,6 +312,10 @@ static int process_args(int argc, char **argv)
       fprintf(stderr, "enabling B extension.\n");
       rv_enable_bext = true;
       break;
+    case 'H':
+      fprintf(stderr, "enabling hypervisor extension.\n");
+      rv_enable_hext = true;
+      break;
     case 'd':
       fprintf(stderr, "enabling dirty update.\n");
       rv_enable_dirty_update = true;

model/prelude.sail

@@ -201,6 +201,17 @@ overload reverse = {reverse_bits_in_byte}
 overload operator / = {quot_positive_round_zero, quot_round_zero}
 overload operator * = {mult_atom, mult_int}
 
+/* helpers for bitvector option type */
+
+val some_or : forall 'n, 'n >= 0 . (option(bits('n)), bits('n)) -> bits('n)
+function some_or(o, d) = match o {
+  Some(v) => v,
+  None()  => d,
+}
+
+val some_or_zero : forall 'n, 'n >= 0. (implicit('n), option(bits('n))) -> bits('n)
+function some_or_zero(n, o) = some_or(o, zeros(n))
+
 /* helper for vector extension
  * 1. EEW between 8 and 64
  * 2. EMUL in vmv<nr>r.v instructions between 1 and 8

model/riscv_csr_hext.sail

@@ -0,0 +1,49 @@
+/*=======================================================================================*/
+/*  This Sail RISC-V architecture model, comprising all files and                        */
+/*  directories except where otherwise noted is subject the BSD                          */
+/*  two-clause license in the LICENSE file.                                              */
+/*                                                                                       */
+/*  SPDX-License-Identifier: BSD-2-Clause                                                */
+/*=======================================================================================*/
+/* Mapping of hypervisor extension CSR addresses to their names. */
+
+/* extra machine registers */
+mapping clause csr_name_map = 0x34B  <-> "mtval2"
+mapping clause csr_name_map = 0x34A  <-> "mtinst"
+
+/* hypervisor trap setup */
+mapping clause csr_name_map = 0x600  <-> "hstatus"
+mapping clause csr_name_map = 0x602  <-> "hedeleg"
+mapping clause csr_name_map = 0x603  <-> "hideleg"
+mapping clause csr_name_map = 0x604  <-> "hie"
+mapping clause csr_name_map = 0x606  <-> "hcounteren"
+mapping clause csr_name_map = 0x607  <-> "hgeie"
+
+/* hypervisor counter/timer virtualization */
+mapping clause csr_name_map = 0x605  <-> "htimedelta"
+mapping clause csr_name_map = 0x615  <-> "htimedeltah"
+
+/* hypervisor config */
+mapping clause csr_name_map = 0x60A  <-> "henvcfg"
+mapping clause csr_name_map = 0x61A  <-> "henvcfgh"
+
+/* hypervisor trap handling */
+mapping clause csr_name_map = 0x643  <-> "htval"
+mapping clause csr_name_map = 0x644  <-> "hip"
+mapping clause csr_name_map = 0x645  <-> "hvip"
+mapping clause csr_name_map = 0x64A  <-> "htinst"
+mapping clause csr_name_map = 0xE12  <-> "hgeip"
+
+/* hypervisor protection and translation */
+mapping clause csr_name_map = 0x680  <-> "hgatp"
+
+/* virtual supervisor registers */
+mapping clause csr_name_map = 0x200  <-> "vsstatus"
+mapping clause csr_name_map = 0x204  <-> "vsie"
+mapping clause csr_name_map = 0x205  <-> "vstvec"
+mapping clause csr_name_map = 0x240  <-> "vsscratch"
+mapping clause csr_name_map = 0x241  <-> "vsepc"
+mapping clause csr_name_map = 0x242  <-> "vscause"
+mapping clause csr_name_map = 0x243  <-> "vstval"
+mapping clause csr_name_map = 0x244  <-> "vsip"
+mapping clause csr_name_map = 0x280  <-> "vsatp"

model/riscv_fetch.sail

@@ -20,16 +20,16 @@ function fetch() -> FetchResult =
     Ext_FetchAddr_Error(e)   => F_Ext_Error(e),
     Ext_FetchAddr_OK(use_pc) => {
       if   (use_pc[0] != bitzero | (use_pc[1] != bitzero & not(extensionEnabled(Ext_Zca))))
-      then F_Error(E_Fetch_Addr_Align(), PC)
+      then F_Error(E_Fetch_Addr_Align(), mem_exception_context(PC, cur_virtualization == V1))
       else match translateAddr(use_pc, Execute()) {
-        TR_Failure(e, _)     => F_Error(e, PC),
+        TR_Failure(e, c, _)     => F_Error(e, c),
         TR_Address(ppclo, _) => {
           /* split instruction fetch into 16-bit granules to handle RVC, as
            * well as to generate precise fault addresses in any fetch
            * exceptions.
            */
           match mem_read(Execute(), ppclo, 2, false, false, false) {
-            MemException(e) => F_Error(e, PC),
+            MemException(e) => F_Error(e, mem_exception_context(PC, cur_virtualization == V1)),
             MemValue(ilo)   => {
               if   isRVC(ilo)
               then F_RVC(ilo)
@@ -40,10 +40,10 @@ function fetch() -> FetchResult =
                   Ext_FetchAddr_Error(e)      => F_Ext_Error(e),
                   Ext_FetchAddr_OK(use_pc_hi) => {
                     match translateAddr(use_pc_hi, Execute()) {
-                      TR_Failure(e, _)     => F_Error(e, PC_hi),
+                      TR_Failure(e, c, _)     => F_Error(e, c),
                       TR_Address(ppchi, _) => {
                         match mem_read(Execute(), ppchi, 2, false, false, false) {
-                          MemException(e) => F_Error(e, PC_hi),
+                          MemException(e) => F_Error(e, mem_exception_context(PC_hi, cur_virtualization == V1)),
                           MemValue(ihi)   => F_Base(append(ihi, ilo))
                         }
                       }

model/riscv_fetch_rvfi.sail

@@ -18,9 +18,9 @@ function fetch() -> FetchResult = {
     Ext_FetchAddr_OK(use_pc) => {
       /* then check PC alignment */
       if   (use_pc[0] != bitzero | (use_pc[1] != bitzero & not(extensionEnabled(Ext_Zca))))
-      then F_Error(E_Fetch_Addr_Align(), PC)
+      then F_Error(E_Fetch_Addr_Align(), mem_exception_context(PC, cur_virtualization == V1))
       else match translateAddr(use_pc, Execute()) {
-        TR_Failure(e, _) => F_Error(e, PC),
+        TR_Failure(e, c, _) => F_Error(e, c),
         TR_Address(_, _) => {
           let i = rvfi_instruction[rvfi_insn];
           rvfi_inst_data[rvfi_insn]   = zero_extend(i);
@@ -33,7 +33,7 @@ function fetch() -> FetchResult = {
               Ext_FetchAddr_Error(e)      => F_Ext_Error(e),
               Ext_FetchAddr_OK(use_pc_hi) =>
                 match translateAddr(use_pc_hi, Execute()) {
-                  TR_Failure(e, _) => F_Error(e, PC),
+                  TR_Failure(e, c, _) => F_Error(e, c),
                   TR_Address(_, _) => F_Base(i)
               }
             }