Hypervisor extension #612
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Hypervisor extension #612
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- Add several hypervisor extension specific CSRs - Add fields to existing machine-level CSRs - Refactor MStatus to use 64 bits and split accesses for RV32
- Impl read_CSR for hypervisor CSRs - Impl write_CSR for hypervisor CSRs - Set initial values for hypervisor CSRs - Set initial value for misa[H]
- Model trap through TrapCause union - Add H-ext exceptions - Add H-ext interrupts - Use TrapContext struct to pass exception exception - Delegate to virtualized mode based on hedeleg
Timmmm
reviewed
Dec 16, 2024
| MPV : 39, | ||
| GVA : 38, | ||
| MBE : 37, | ||
| SBE : 36, | ||
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| // The SXL and UXL fields don't exist on RV32, so they are modelled | ||
| // via explicit getters and setters; see below. |
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radimkrcmar
reviewed
Dec 18, 2024
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| function get_hstatus_VSXL(h : Hstatus) -> arch_xlen = { | ||
| if sizeof(xlen) == 32 | ||
| then arch_to_bits(RV32) |
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"When HSXLEN=32, VSXL field does not exist." The spec isn't terribly clear on what that means, but I'd assume WPRI, so the read should be 0b00 and not 0b01.
I see this code was inspired by the UXL field of the sstatus register, so I'll send a patch for that, unless you know something I missed.
Thanks.
Timmmm
reviewed
Dec 18, 2024
| register mstatush : Mstatush | ||
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| bitfield Mstatus : xlenbits = { | ||
| bitfield Mstatus : bits(64) = { | ||
| SD : xlen - 1, |
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This is a version of the hypervisor extension ported on a more recent version of the model. Feel welcome to provide any feedback
In order to verify the modifications & additions to this version of the model, the following tests are used:
By booting Linux on top of Xvisor on top of OpenSBI(My current setup requires terminal input which is not already implemented nor part of the hypervisor spec.)PS I closed #334 in favor of this pull request.