[tests] Add zfinx and zhinx hardware tests

software/Makefile

@@ -35,21 +35,27 @@ clean-halide-apps:
 TESTS := $(addprefix bin/,$(rtl_mempool_tests))
 
 define rtl_mempool_tests_template
-
 TESTS_$(1) := $(addprefix bin/,$($(1)_mempool_tests))
 
 $$(TESTS_$(1)): bin/$(1)-mempool-%: $(TESTS_DIR)/$(1)/%.S $(LINKER_SCRIPT)
 	mkdir -p $$(shell dirname $$@)
 	$$(RISCV_CC) $$(RISCV_CCFLAGS_TESTS) -T$$(RUNTIME_DIR)/link.ld $$< -o $$@
 	$$(RISCV_STRIP) $$@ -g -S -d --strip-debug
 	$$(RISCV_OBJDUMP) $(RISCV_OBJDUMP_FLAGS) -D $$@ > $$@.dump
-
 endef
 
+ifeq ($(COMPILER), llvm)
+$(eval $(call rtl_mempool_tests_template,rv32ui))
+$(eval $(call rtl_mempool_tests_template,rv32um))
+$(eval $(call rtl_mempool_tests_template,rv32ua))
+$(eval $(call rtl_mempool_tests_template,rv32uzfinx))
+$(eval $(call rtl_mempool_tests_template,rv32uzhinx))
+else
 $(eval $(call rtl_mempool_tests_template,rv32ui))
 $(eval $(call rtl_mempool_tests_template,rv32um))
 $(eval $(call rtl_mempool_tests_template,rv32ua))
 $(eval $(call rtl_mempool_tests_template,rv32uxpulpimg))
+endif
 
 test: update_opcodes $(TESTS)
 

software/riscv-tests/isa/Makefile

@@ -26,6 +26,8 @@ include $(src_dir)/rv32um/Makefrag
 include $(src_dir)/rv32ua/Makefrag
 include $(src_dir)/rv32uf/Makefrag
 include $(src_dir)/rv32ud/Makefrag
+include $(src_dir)/rv32uzfinx/Makefrag
+include $(src_dir)/rv32uzhinx/Makefrag
 ifneq ($(COMPILER), llvm)
 include $(src_dir)/rv32si/Makefrag
 include $(src_dir)/rv32mi/Makefrag
@@ -52,7 +54,7 @@ ifeq ($(COMPILER), llvm)
 	RISCV_TARGET ?= riscv$(XLEN)-unknown-elf
 	RISCV_LLVM_TARGET  ?= --target=$(RISCV_TARGET) --sysroot=$(GCC_INSTALL_DIR)/$(RISCV_TARGET) --gcc-toolchain=$(GCC_INSTALL_DIR)
 	RISCV_CC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles $(RISCV_LLVM_TARGET)
-	RISCV_OBJDUMP_FLAGS += --mattr=+m,+a,+xpulpmacsi,+xpulppostmod,+xpulpvect,+xpulpvectshufflepack,+f
+	RISCV_OBJDUMP_FLAGS += --mattr=+m,+a,+f,+zfinx,+xpulpmacsi,+xpulppostmod,+xpulpvect,+xpulpvectshufflepack
 	RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump $(RISCV_OBJDUMP_FLAGS) --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data
 else
 	# Default compilation with GCC
@@ -123,7 +125,10 @@ $(eval $(call compile_template,rv32um,-march=rv32g -mabi=ilp32))
 $(eval $(call compile_template,rv32ua,-march=rv32g -mabi=ilp32))
 $(eval $(call compile_template,rv32uf,-march=rv32g -mabi=ilp32))
 $(eval $(call compile_template,rv32ud,-march=rv32g -mabi=ilp32))
-RISCV_ARCH ?= rv$(XLEN)ima_xpulppostmod_xpulpmacsi_xpulpvect_xpulpvectshufflepack_xmempool
+RISCV_ARCH := rv$(XLEN)ima_zfinx_zhinx_zquarterinx_zvechalfinx_zexpauxvechalfinx
+RISCV_ARCH := $(RISCV_ARCH)_xpulppostmod_xpulpmacsi_xpulpvect_xpulpvectshufflepack_xmempool
+$(eval $(call compile_template,rv32uzfinx,-march=$(RISCV_ARCH) -mabi=ilp32))
+$(eval $(call compile_template,rv32uzhinx,-march=$(RISCV_ARCH) -mabi=ilp32))
 $(eval $(call compile_template,rv32uxpulpimg,-march=$(RISCV_ARCH) -mabi=ilp32))
 else
 $(eval $(call compile_template,rv32ui,-march=rv32g -mabi=ilp32))

software/riscv-tests/isa/macros/scalar/test_macros.h

@@ -496,6 +496,19 @@ test_ ## testnum: \
       inst x0, x1, x2; \
     )
 
+#-----------------------------------------------------------------------
+# Tests for instructions with 3 register operands & 1 dst register
+#-----------------------------------------------------------------------
+
+#define TEST_RRR_PLUSD_OP( testnum, inst, result, val1, val2, val3) \
+    TEST_CASE( testnum, x14, result, \
+      li  x1, MASK_XLEN(val1); \
+      li  x2, MASK_XLEN(val2); \
+      li x14, MASK_XLEN(val3); \
+      inst x14, x1, x2, x14; \
+    )
+
+
 #-----------------------------------------------------------------------
 # Tests for Xpulpimg instructions with 2 register operands (rd and rs1)
 # and a 6-bit unsigned immediate input

software/riscv-tests/isa/rv32ud/Makefrag

@@ -2,7 +2,6 @@
 # Makefrag for rv32ud tests
 #-----------------------------------------------------------------------
 
-ifeq ($(COMPILER), llvm)
 rv32ud_sc_tests = fadd \
                   fdiv \
                   fclass \
@@ -13,18 +12,6 @@ rv32ud_sc_tests = fadd \
                   fmin \
                   ldst \
                   recoding
-else
-rv32ud_sc_tests = fadd \
-                  fdiv \
-                  fclass \
-                  fcmp \
-                  fcvt \
-                  fcvt_w \
-                  fmadd \
-                  fmin \
-                  ldst \
-                  recoding
-endif
 
 # TODO: use this line instead of the last of the previous once move and structural tests have been implemented
 #        ldst move structural recoding \

software/riscv-tests/isa/rv32uf/Makefrag

@@ -2,19 +2,6 @@
 # Makefrag for rv32uf tests
 #-----------------------------------------------------------------------
 
-ifeq ($(COMPILER), llvm)
-rv32uf_sc_tests = fadd \
-                  fdiv \
-                  fclass \
-                  fcmp \
-                  fcvt \
-                  fcvt_w \
-                  fmadd \
-                  fmin \
-                  ldst \
-                  move \
-                  recoding
-else
 rv32uf_sc_tests = fadd \
                   fdiv \
                   fclass \
@@ -26,7 +13,6 @@ rv32uf_sc_tests = fadd \
                   ldst \
                   move \
                   recoding
-endif
 
 rv32uf_p_tests = $(addprefix rv32uf-p-, $(rv32uf_sc_tests))
 rv32uf_v_tests = $(addprefix rv32uf-v-, $(rv32uf_sc_tests))

software/riscv-tests/isa/rv32uzfinx/Makefrag

@@ -0,0 +1,16 @@
+#=======================================================================
+# Makefrag for rv32uzfinx tests
+#-----------------------------------------------------------------------
+
+ifeq ($(COMPILER), llvm)
+rv32uzfinx_sc_tests = \
+                      fadd \
+                      fdiv \
+                      fmadd \
+                      fmin \
+                      fsgnj
+endif
+
+rv32uzfinx_p_tests = $(addprefix rv32uzfinx-p-, $(rv32uzfinx_sc_tests))
+
+# Zfinx extensions are not tested on Spike

software/riscv-tests/isa/rv32uzfinx/fadd.S

@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fadd.S
+#-----------------------------------------------------------------------------
+#
+# Test add instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  fadd.s, 0x40600000, 0x40200000, 0x3F800000 );
+  TEST_RR_OP( 3,  fadd.s, 0xC49A4000, 0xC49A6333, 0x3F8CCCCD );
+  TEST_RR_OP( 4,  fadd.s, 0x40490FDB, 0x40490FDB, 0x322BCC77 );
+
+  TEST_RR_OP( 5,  fsub.s, 0x3FC00000, 0x40200000, 0x3F800000 );
+  TEST_RR_OP( 6,  fsub.s, 0xC49A4000, 0xC49A6333, 0xBF8CCCCD );
+  TEST_RR_OP( 7,  fsub.s, 0x40490FDB, 0x40490FDB, 0x322BCC77 );
+
+  TEST_RR_OP( 8,  fmul.s, 0x40200000, 0x40200000, 0x3F800000 );
+  TEST_RR_OP( 9,  fmul.s, 0x44A9D385, 0xC49A6333, 0xBF8CCCCD );
+  TEST_RR_OP(10,  fmul.s, 0x3306EE2D, 0x40490FDB, 0x322BCC77 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END

software/riscv-tests/isa/rv32uzfinx/fdiv.S

@@ -0,0 +1,35 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fdiv.S
+#-----------------------------------------------------------------------------
+#
+# Test add instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  fdiv.s, 0x3F93EEE0, 0x40490FDB, 0x402DF854 );
+  TEST_RR_OP( 3,  fdiv.s, 0xBF7FC5A2, 0xC49A4000, 0x449A6333 );
+  TEST_RR_OP( 4,  fdiv.s, 0x40490FDB, 0x40490FDB, 0x3F800000 );
+
+  TEST_R_OP( 5,  fsqrt.s, 0x3FE2DFC5, 0x40490FDB );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END

software/riscv-tests/isa/rv32uzfinx/fmadd.S

@@ -0,0 +1,45 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fmadd.S
+#-----------------------------------------------------------------------------
+#
+# Test add instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RRR_PLUSD_OP( 2,  fmadd.s, 0x40600000, 0x3F800000, 0x40200000, 0x3F800000 ); #   3.5,  1.0,     2.5,  1.0
+  TEST_RRR_PLUSD_OP( 3,  fmadd.s, 0x449A8666, 0xBF800000, 0xC49A6333, 0x3F8CCCCD ); #1236.2, -1.0, -1235.1,  1.1
+  TEST_RRR_PLUSD_OP( 4,  fmadd.s, 0xC1400000, 0x40000000, 0xC0A00000, 0xC0000000 ); # -12.0,  2.0,    -5.0, -2.0
+
+  TEST_RRR_PLUSD_OP( 5,  fnmadd.s, 0xC0600000, 0x3F800000, 0x40200000, 0x3F800000 ); #   -3.5,  1.0,     2.5,  1.0
+  TEST_RRR_PLUSD_OP( 6,  fnmadd.s, 0xC49A8666, 0xBF800000, 0xC49A6333, 0x3F8CCCCD ); #-1236.2, -1.0, -1235.1,  1.1
+  TEST_RRR_PLUSD_OP( 7,  fnmadd.s, 0x41400000, 0x40000000, 0xC0A00000, 0xC0000000 ); #   12.0,  2.0,    -5.0, -2.0
+
+  TEST_RRR_PLUSD_OP( 8,  fmsub.s, 0x3FC00000, 0x3F800000, 0x40200000, 0x3F800000 ); #   -1.5,  1.0,     2.5,  1.0
+  TEST_RRR_PLUSD_OP( 9,  fmsub.s, 0x449A4000, 0xBF800000, 0xC49A6333, 0x3F8CCCCD ); # 1234.0, -1.0, -1235.1,  1.1
+  TEST_RRR_PLUSD_OP( 10,  fmsub.s, 0xC1000000, 0x40000000, 0xC0A00000, 0xC0000000 ); #   -8.0,  2.0,    -5.0, -2.0
+
+  TEST_RRR_PLUSD_OP( 11,  fnmsub.s, 0xBFC00000, 0x3F800000, 0x40200000, 0x3F800000 ); #   -1.5,  1.0,     2.5,  1.0
+  TEST_RRR_PLUSD_OP( 12,  fnmsub.s, 0xC49A4000, 0xBF800000, 0xC49A6333, 0x3F8CCCCD ); #-1234.0, -1.0, -1235.1,  1.1
+  TEST_RRR_PLUSD_OP( 13,  fnmsub.s, 0x41000000, 0x40000000, 0xC0A00000, 0xC0000000 ); #    8.0,  2.0,    -5.0, -2.0
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END

software/riscv-tests/isa/rv32uzfinx/fmin.S

@@ -0,0 +1,43 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fmin.S
+#-----------------------------------------------------------------------------
+#
+# Test add instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  fmin.s, 0x3F800000, 0x40200000, 0x3F800000 );
+  TEST_RR_OP( 3,  fmin.s, 0xC49A6333, 0xC49A6333, 0x3F8CCCCD );
+  TEST_RR_OP( 4,  fmin.s, 0xC49A6333, 0x3F8CCCCD, 0xC49A6333 );
+  TEST_RR_OP( 5,  fmin.s, 0xC49A6333, 0x7FC00000, 0xC49A6333 );
+  TEST_RR_OP( 6,  fmin.s, 0x322BCC77, 0x40490FDB, 0x322BCC77 );
+  TEST_RR_OP( 7,  fmin.s, 0xC0000000, 0xBF800000, 0xC0000000 );
+
+  TEST_RR_OP( 8,  fmax.s, 0x40200000, 0x40200000, 0x3F800000 );
+  TEST_RR_OP( 9,  fmax.s, 0x3F8CCCCD, 0xC49A6333, 0x3F8CCCCD );
+  TEST_RR_OP(10,  fmax.s, 0x3F8CCCCD, 0x3F8CCCCD, 0xC49A6333 );
+  TEST_RR_OP(11,  fmax.s, 0xC49A6333, 0x7FC00000, 0xC49A6333 );
+  TEST_RR_OP(12,  fmax.s, 0x40490FDB, 0x40490FDB, 0x322BCC77 );
+  TEST_RR_OP(13,  fmax.s, 0xBF800000, 0xBF800000, 0xC0000000 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END

software/riscv-tests/isa/rv32uzfinx/fsgnj.S

@@ -0,0 +1,41 @@
+# See LICENSE for license details.
+
+#*****************************************************************************
+# fsgnj.S
+#-----------------------------------------------------------------------------
+#
+# Test add instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV32U
+RVTEST_CODE_BEGIN
+
+  #-------------------------------------------------------------
+  # Arithmetic tests
+  #-------------------------------------------------------------
+
+  TEST_RR_OP( 2,  fsgnj.s, 0x40200000, 0x40200000, 0x3F800000 );
+  TEST_RR_OP( 3,  fsgnj.s, 0x449A6333, 0xC49A6333, 0x3F8CCCCD );
+  TEST_RR_OP( 4,  fsgnj.s, 0xBF8CCCCD, 0x3F8CCCCD, 0xC49A6333 );
+
+  TEST_RR_OP( 5,  fsgnjn.s, 0xC0200000, 0x40200000, 0x3F800000 );
+  TEST_RR_OP( 6,  fsgnjn.s, 0xC49A6333, 0xC49A6333, 0x3F8CCCCD );
+  TEST_RR_OP( 7,  fsgnjn.s, 0x3F8CCCCD, 0x3F8CCCCD, 0xC49A6333 );
+
+  TEST_RR_OP( 8,  fsgnjx.s, 0x40200000, 0x40200000, 0x3F800000 );
+  TEST_RR_OP( 9,  fsgnjx.s, 0xC49A6333, 0xC49A6333, 0x3F8CCCCD );
+  TEST_RR_OP(10,  fsgnjx.s, 0xBF8CCCCD, 0x3F8CCCCD, 0xC49A6333 );
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+RVTEST_DATA_END

software/riscv-tests/isa/rv32uzhinx/Makefrag

@@ -0,0 +1,16 @@
+#=======================================================================
+# Makefrag for rv32uzfinx tests
+#-----------------------------------------------------------------------
+
+ifeq ($(COMPILER), llvm)
+rv32uzhinx_sc_tests = \
+                      fadd_h \
+                      fdiv_h \
+                      fmadd_h \
+                      fmin_h \
+                      fsgnj_h
+endif
+
+rv32uzhinx_p_tests = $(addprefix rv32uzhinx-p-, $(rv32uzhinx_sc_tests))
+
+# Zhinx extensions are not tested on Spike