[tests] Compile RISCV tests with LLVM

Makefile

@@ -110,7 +110,7 @@ riscv-isa-sim: update_opcodes
 test: build_test
 	export PATH=$(ISA_SIM_INSTALL_DIR)/bin:$$PATH; \
 	make -C $(RISCV_TESTS_DIR)/isa run && \
-	config=minpool COMPILER=gcc make -C $(SOFTWARE_DIR) test && \
+	config=minpool make -C $(SOFTWARE_DIR) test && \
 	config=minpool make -C hardware verilate_test
 
 build_test: update_opcodes

software/riscv-tests/env/v/vm.c

@@ -171,8 +171,9 @@ void handle_fault(uintptr_t addr, uintptr_t cause)
 
   user_llpt[addr/PGSIZE] = new_pte;
   flush_page(addr);
-
+#ifndef LLVM
   __builtin___clear_cache(0,0);
+#endif
 }
 
 void handle_trap(trapframe_t* tf)

software/riscv-tests/isa/Makefile

@@ -6,24 +6,30 @@ XLEN ?= 32
 
 src_dir := .
 
+# XLEN 64
 ifeq ($(XLEN),64)
-include $(src_dir)/rv64ui/Makefrag
-include $(src_dir)/rv64uc/Makefrag
-include $(src_dir)/rv64um/Makefrag
-include $(src_dir)/rv64ua/Makefrag
-include $(src_dir)/rv64uf/Makefrag
-include $(src_dir)/rv64ud/Makefrag
-include $(src_dir)/rv64si/Makefrag
-include $(src_dir)/rv64mi/Makefrag
+	include $(src_dir)/rv64ui/Makefrag
+	include $(src_dir)/rv64uc/Makefrag
+	include $(src_dir)/rv64um/Makefrag
+	include $(src_dir)/rv64ua/Makefrag
+	include $(src_dir)/rv64uf/Makefrag
+	include $(src_dir)/rv64ud/Makefrag
+	ifneq ($(COMPILER), llvm)
+	include $(src_dir)/rv64si/Makefrag
+	include $(src_dir)/rv64mi/Makefrag
+	endif
 endif
+# XLEN 32
 include $(src_dir)/rv32ui/Makefrag
 include $(src_dir)/rv32uc/Makefrag
 include $(src_dir)/rv32um/Makefrag
 include $(src_dir)/rv32ua/Makefrag
 include $(src_dir)/rv32uf/Makefrag
 include $(src_dir)/rv32ud/Makefrag
+ifneq ($(COMPILER), llvm)
 include $(src_dir)/rv32si/Makefrag
 include $(src_dir)/rv32mi/Makefrag
+endif
 include $(src_dir)/rv32uxpulpimg/Makefrag
 
 default: all
@@ -35,13 +41,27 @@ default: all
 MEMPOOL_DIR       := $(shell git rev-parse --show-toplevel 2>/dev/null || echo $$MEMPOOL_DIR)
 INSTALL_DIR       ?= $(MEMPOOL_DIR)/install
 GCC_INSTALL_DIR   ?= $(INSTALL_DIR)/riscv-gcc
+LLVM_INSTALL_DIR  ?= $(INSTALL_DIR)/llvm
 SPIKE_INSTALL_DIR ?= $(INSTALL_DIR)/riscv-isa-sim
+RISCV_SIM 				?= $(SPIKE_INSTALL_DIR)/bin/spike
+
+
+ifeq ($(COMPILER), llvm)
+	RISCV_PREFIX ?= $(LLVM_INSTALL_DIR)/bin/llvm-
+	RISCV_CC ?= $(LLVM_INSTALL_DIR)/bin/clang
+	RISCV_TARGET ?= riscv$(XLEN)-unknown-elf
+	RISCV_LLVM_TARGET  ?= --target=$(RISCV_TARGET) --sysroot=$(GCC_INSTALL_DIR)/$(RISCV_TARGET) --gcc-toolchain=$(GCC_INSTALL_DIR)
+	RISCV_CC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles $(RISCV_LLVM_TARGET)
+	RISCV_OBJDUMP_FLAGS += --mattr=+m,+a,+xpulpmacsi,+xpulppostmod,+xpulpvect,+xpulpvectshufflepack,+f
+	RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump $(RISCV_OBJDUMP_FLAGS) --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data
+else
+	# Default compilation with GCC
+	RISCV_PREFIX ?= $(GCC_INSTALL_DIR)/bin/riscv$(XLEN)-unknown-elf-
+	RISCV_CC ?= $(RISCV_PREFIX)gcc
+	RISCV_CC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
+	RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump --disassembler-option="march=rv32gXpulpimg" --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data
+endif
 
-RISCV_PREFIX ?= $(GCC_INSTALL_DIR)/bin/riscv$(XLEN)-unknown-elf-
-RISCV_GCC ?= $(RISCV_PREFIX)gcc
-RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles
-RISCV_OBJDUMP ?= $(RISCV_PREFIX)objdump --disassembler-option="march=rv32gXpulpimg" --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data
-RISCV_SIM ?= $(SPIKE_INSTALL_DIR)/bin/spike
 
 vpath %.S $(src_dir)
 
@@ -59,26 +79,53 @@ vpath %.S $(src_dir)
 	PATH="$(MEMPOOL_DIR)/install/riscv-isa-sim/bin:$$PATH"; \
 	$(RISCV_SIM) --isa=rv32gc $< 2> $@
 
+ifeq ($(COMPILER), llvm)
+
 define compile_template
+$$($(1)_p_tests): $(1)-p-%: $(1)/%.S
+	$$(RISCV_CC) $(2) $$(RISCV_CC_OPTS) -DLLVM -I$(src_dir)/../env/p -I$(src_dir)/macros/scalar -T$(src_dir)/../env/p/link.ld $$< -o $$@
+$(1)_tests += $$($(1)_p_tests)
+
+$(1)_tests_dump = $$(addsuffix .dump, $$($(1)_tests))
+$(1): $$($(1)_tests_dump)
 
+.PHONY: $(1)
+tests += $$($(1)_tests)
+endef
+
+else
+
+define compile_template
 $$($(1)_p_tests): $(1)-p-%: $(1)/%.S
-	$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -I$(src_dir)/../env/p -I$(src_dir)/macros/scalar -T$(src_dir)/../env/p/link.ld $$< -o $$@
+	$$(RISCV_CC) $(2) $$(RISCV_CC_OPTS) -I$(src_dir)/../env/p -I$(src_dir)/macros/scalar -T$(src_dir)/../env/p/link.ld $$< -o $$@
 $(1)_tests += $$($(1)_p_tests)
 
 $$($(1)_v_tests): $(1)-v-%: $(1)/%.S
-	$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) -DENTROPY=0x$$(shell echo \$$@ | md5sum | cut -c 1-7) -std=gnu99 -O2 -I$(src_dir)/../env/v -I$(src_dir)/macros/scalar -T$(src_dir)/../env/v/link.ld $(src_dir)/../env/v/entry.S $(src_dir)/../env/v/*.c $$< -o $$@
+	$$(RISCV_CC) $(2) $$(RISCV_CC_OPTS) -DENTROPY=0x$$(shell echo \$$@ | md5sum | cut -c 1-7) -std=gnu99 -O2 -I$(src_dir)/../env/v -I$(src_dir)/macros/scalar -T$(src_dir)/../env/v/link.ld $(src_dir)/../env/v/entry.S $(src_dir)/../env/v/*.c $$< -o $$@
 $(1)_tests += $$($(1)_v_tests)
 
 $(1)_tests_dump = $$(addsuffix .dump, $$($(1)_tests))
-
 $(1): $$($(1)_tests_dump)
 
 .PHONY: $(1)
-
 tests += $$($(1)_tests)
-
 endef
 
+endif
+
+# Single precision
+
+# Xpulpimg
+ifeq ($(COMPILER),llvm)
+$(eval $(call compile_template,rv32ui,-march=rv32g -mabi=ilp32))
+$(eval $(call compile_template,rv32uc,-march=rv32g -mabi=ilp32))
+$(eval $(call compile_template,rv32um,-march=rv32g -mabi=ilp32))
+$(eval $(call compile_template,rv32ua,-march=rv32g -mabi=ilp32))
+$(eval $(call compile_template,rv32uf,-march=rv32g -mabi=ilp32))
+$(eval $(call compile_template,rv32ud,-march=rv32g -mabi=ilp32))
+RISCV_ARCH ?= rv$(XLEN)ima_xpulppostmod_xpulpmacsi_xpulpvect_xpulpvectshufflepack_xmempool
+$(eval $(call compile_template,rv32uxpulpimg,-march=$(RISCV_ARCH) -mabi=ilp32))
+else
 $(eval $(call compile_template,rv32ui,-march=rv32g -mabi=ilp32))
 $(eval $(call compile_template,rv32uc,-march=rv32g -mabi=ilp32))
 $(eval $(call compile_template,rv32um,-march=rv32g -mabi=ilp32))
@@ -88,6 +135,9 @@ $(eval $(call compile_template,rv32ud,-march=rv32g -mabi=ilp32))
 $(eval $(call compile_template,rv32si,-march=rv32g -mabi=ilp32))
 $(eval $(call compile_template,rv32mi,-march=rv32g -mabi=ilp32))
 $(eval $(call compile_template,rv32uxpulpimg,-march=rv32gXpulpimg -mabi=ilp32))
+endif
+
+# Double precision
 ifeq ($(XLEN),64)
 $(eval $(call compile_template,rv64ui,-march=rv64g -mabi=lp64))
 $(eval $(call compile_template,rv64uc,-march=rv64g -mabi=lp64))

software/riscv-tests/isa/macros/scalar/test_macros.h

@@ -1075,10 +1075,17 @@ test_ ## testnum: \
 # Tests floating-point instructions
 #-----------------------------------------------------------------------
 
+#ifdef LLVM
+#define qNaNf NaN
+#define sNaNf NaN
+#define qNaN NaN
+#define sNaN NaN
+#else
 #define qNaNf 0f:7fc00000
 #define sNaNf 0f:7f800001
 #define qNaN 0d:7ff8000000000000
 #define sNaN 0d:7ff0000000000001
+#endif
 
 #define TEST_FP_OP_S_INTERNAL( testnum, flags, result, val1, val2, val3, code... ) \
 test_ ## testnum: \

software/riscv-tests/isa/rv32mi/shamt.S

@@ -21,7 +21,11 @@ RVTEST_CODE_BEGIN
 
   TEST_PASSFAIL
 
+#ifdef LLVM
+.weak mtvec_handler
+#else
 .global mtvec_handler
+#endif
 mtvec_handler:
   # Trapping on test 3 is good.
   # Note that since the test didn't complete, TESTNUM is smaller by 1.

software/riscv-tests/isa/rv32ua/Makefrag

@@ -9,4 +9,8 @@ rv32ua_sc_tests = \
 rv32ua_p_tests = $(addprefix rv32ua-p-, $(rv32ua_sc_tests))
 rv32ua_v_tests = $(addprefix rv32ua-v-, $(rv32ua_sc_tests))
 
+ifeq ($(COMPILER), llvm)
+spike32_tests += $(rv32ua_p_tests)
+else
 spike32_tests += $(rv32ua_p_tests) $(rv32ua_v_tests)
+endif

software/riscv-tests/isa/rv32uc/Makefrag

@@ -8,4 +8,8 @@ rv32uc_sc_tests = \
 rv32uc_p_tests = $(addprefix rv32uc-p-, $(rv32uc_sc_tests))
 rv32uc_v_tests = $(addprefix rv32uc-v-, $(rv32uc_sc_tests))
 
+ifeq ($(COMPILER), llvm)
+spike32_tests += $(rv32uc_p_tests)
+else
 spike32_tests += $(rv32uc_p_tests) $(rv32uc_v_tests)
+endif

software/riscv-tests/isa/rv32ud/Makefrag

@@ -2,14 +2,38 @@
 # Makefrag for rv32ud tests
 #-----------------------------------------------------------------------
 
-rv32ud_sc_tests = \
-	fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \
-	ldst recoding \
+ifeq ($(COMPILER), llvm)
+rv32ud_sc_tests = fadd \
+                  fdiv \
+                  fclass \
+                  fcmp \
+                  fcvt \
+                  fcvt_w \
+                  fmadd \
+                  fmin \
+                  ldst \
+                  recoding
+else
+rv32ud_sc_tests = fadd \
+                  fdiv \
+                  fclass \
+                  fcmp \
+                  fcvt \
+                  fcvt_w \
+                  fmadd \
+                  fmin \
+                  ldst \
+                  recoding
+endif
 
 # TODO: use this line instead of the last of the previous once move and structural tests have been implemented
 #        ldst move structural recoding \
 
 rv32ud_p_tests = $(addprefix rv32ud-p-, $(rv32ud_sc_tests))
 rv32ud_v_tests = $(addprefix rv32ud-v-, $(rv32ud_sc_tests))
 
+ifeq ($(COMPILER), llvm)
+spike32_tests += $(rv32ud_p_tests)
+else
 spike32_tests += $(rv32ud_p_tests) $(rv32ud_v_tests)
+endif

software/riscv-tests/isa/rv32uf/Makefrag

@@ -2,11 +2,37 @@
 # Makefrag for rv32uf tests
 #-----------------------------------------------------------------------
 
-rv32uf_sc_tests = \
-	fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \
-	ldst move recoding \
+ifeq ($(COMPILER), llvm)
+rv32uf_sc_tests = fadd \
+                  fdiv \
+                  fclass \
+                  fcmp \
+                  fcvt \
+                  fcvt_w \
+                  fmadd \
+                  fmin \
+                  ldst \
+                  move \
+                  recoding
+else
+rv32uf_sc_tests = fadd \
+                  fdiv \
+                  fclass \
+                  fcmp \
+                  fcvt \
+                  fcvt_w \
+                  fmadd \
+                  fmin \
+                  ldst \
+                  move \
+                  recoding
+endif
 
 rv32uf_p_tests = $(addprefix rv32uf-p-, $(rv32uf_sc_tests))
 rv32uf_v_tests = $(addprefix rv32uf-v-, $(rv32uf_sc_tests))
 
+ifeq ($(COMPILER), llvm)
+spike32_tests += $(rv32uf_p_tests)
+else
 spike32_tests += $(rv32uf_p_tests) $(rv32uf_v_tests)
+endif

software/riscv-tests/isa/rv32ui/Makefrag

@@ -24,4 +24,8 @@ rv32ui_sc_tests = \
 rv32ui_p_tests = $(addprefix rv32ui-p-, $(rv32ui_sc_tests))
 rv32ui_v_tests = $(addprefix rv32ui-v-, $(rv32ui_sc_tests))
 
+ifeq ($(COMPILER), llvm)
+spike32_tests += $(rv32ui_p_tests)
+else
 spike32_tests += $(rv32ui_p_tests) $(rv32ui_v_tests)
+endif

software/riscv-tests/isa/rv32um/Makefrag

@@ -10,4 +10,8 @@ rv32um_sc_tests = \
 rv32um_p_tests = $(addprefix rv32um-p-, $(rv32um_sc_tests))
 rv32um_v_tests = $(addprefix rv32um-v-, $(rv32um_sc_tests))
 
+ifeq ($(COMPILER), llvm)
+spike32_tests += $(rv32um_p_tests)
+else
 spike32_tests += $(rv32um_p_tests) $(rv32um_v_tests)
+endif

software/riscv-tests/isa/rv32uxpulpimg/Makefrag

@@ -2,14 +2,45 @@
 # Makefrag for rv32uxpulpimg tests
 #-----------------------------------------------------------------------
 
+ifeq ($(COMPILER), llvm)
 rv32uxpulpimg_sc_tests = \
   p_lb_irpost p_lbu_irpost p_lh_irpost p_lhu_irpost p_lw_irpost \
   p_lb_rrpost p_lbu_rrpost p_lh_rrpost p_lhu_rrpost p_lw_rrpost \
   p_lb_rr p_lbu_rr p_lh_rr p_lhu_rr p_lw_rr \
   p_sb_irpost p_sh_irpost p_sw_irpost \
   p_sb_rrpost p_sh_rrpost p_sw_rrpost \
   p_sb_rr p_sh_rr p_sw_rr \
-	p_abs \
+  p_mac p_msu \
+  pv_add \
+  pv_sub \
+  pv_avg pv_avgu \
+  pv_min pv_minu \
+  pv_max pv_maxu \
+  pv_srl \
+  pv_sra \
+  pv_sll \
+  pv_or \
+  pv_xor \
+  pv_and \
+  pv_abs \
+  pv_extract pv_extractu \
+  pv_insert \
+  pv_dotup \
+  pv_dotusp \
+  pv_dotsp \
+  pv_sdotup \
+  pv_sdotusp \
+  pv_sdotsp \
+  pv_shuffle2
+else
+rv32uxpulpimg_sc_tests = \
+  p_lb_irpost p_lbu_irpost p_lh_irpost p_lhu_irpost p_lw_irpost \
+  p_lb_rrpost p_lbu_rrpost p_lh_rrpost p_lhu_rrpost p_lw_rrpost \
+  p_lb_rr p_lbu_rr p_lh_rr p_lhu_rr p_lw_rr \
+  p_sb_irpost p_sh_irpost p_sw_irpost \
+  p_sb_rrpost p_sh_rrpost p_sw_rrpost \
+  p_sb_rr p_sh_rr p_sw_rr \
+  p_abs \
   p_slet p_sletu \
   p_min p_minu \
   p_max p_maxu \
@@ -41,9 +72,14 @@ rv32uxpulpimg_sc_tests = \
   pv_sdotup \
   pv_sdotusp \
   pv_sdotsp \
-  pv_shuffle2 \
+  pv_shuffle2
+endif
 
 rv32uxpulpimg_p_tests = $(addprefix rv32uxpulpimg-p-, $(rv32uxpulpimg_sc_tests))
 rv32uxpulpimg_v_tests = $(addprefix rv32uxpulpimg-v-, $(rv32uxpulpimg_sc_tests))
 
+ifeq ($(COMPILER), llvm)
+spike32_tests += $(rv32uxpulpimg_p_tests)
+else
 spike32_tests += $(rv32uxpulpimg_p_tests) $(rv32uxpulpimg_v_tests)
+endif

software/riscv-tests/isa/rv64mi/access.S

@@ -43,7 +43,11 @@ RVTEST_CODE_BEGIN
   TEST_PASSFAIL
 
   .align 2
+  #ifdef LLVM
+  .weak mtvec_handler
+  #else
   .global mtvec_handler
+  #endif
 mtvec_handler:
   li a0, 2
   beq TESTNUM, a0, 2f

software/riscv-tests/isa/rv64mi/breakpoint.S

@@ -101,7 +101,11 @@ RVTEST_CODE_BEGIN
   TEST_PASSFAIL
 
   .align 2
+  #ifdef LLVM
+  .weak mtvec_handler
+  #else
   .global mtvec_handler
+  #endif
 mtvec_handler:
   # Only even-numbered tests should trap.
   andi t0, TESTNUM, 1