Load/Store cross, reset polarity fix, other cleanup. Integrated with SCR1 demo

Integrated with SCR1 demo
Fixed reset polarity to be active low to match with rstn naming
Updated documentation to better describe pipeline whiteboxing connection considerations
Fixed bug with decoder bits for instruction length found by Muneeb
Updated store instructions’ to_string() to have clock cycle
Created a common string_base() method for common to_string() chunk
Instantiated inst_same_regs_cg, rs1/rs2/rd_bins_cg and added sample_from_subclass() method
Added different load and store cross coverage with different bases and offsets
Other minor clean-up and documentation
Regression passing

Instruction history and read-after-write hazard cross coverage

• instruction history and read-after-write hazard/forwarding cross coverage integrated and tested
• updated docs to include instruction history and raw cross info

v0.2.0

Integrated register file monitoring and rs1/2 value association with instructions. Documentation updated accordingly and recommending that the instruction is tapped upon commit.

Improved UVM unit tests

• updated/clarified docs, riscv-test hex_file_analyzer hex file gen section
• beefed up i32_agent uvc_env unit tests
• added uvm test unit test
• passing local Jenkins for ius and questa

Intial release with some Users' guide fixes/updates

Same as v0.1.1 but with some documentation updates/fixes.

Intial release with uvm test files

This adds some files needed for creating a new uvm test with riscv-vip. These files were missing from v0.1.0

Initial release.

Initial release, should work as documented. For RV32I, has coverage of immediate fields and instructions, debug/decode trace and UVM integration into an existing non-uvm environment.