Last Level Cache Design and Simulation

This project focuses on designing and simulating a Last Level Cache (LLC) for processors, addressing the challenge of memory systems lagging behind high-speed processors. By implementing a caching mechanism, critical data and instructions are stored closer to the processor for faster access. This project is fully parameterizable and can be easily adapted to changes in the given specifications.

Key Features

L2 Cache Specifications

• Total Capacity: 16MB
• Byte Line: 64 bytes
• Associativity: 16-way set
• Coherence Protocol: MESI
• Replacement Policy: Pseudo-LRU

L1 Cache Specifications

• Byte Line: 64 bytes
• Associativity: 4-way set
• Write Policy: Write-once (initial write-through, subsequent write-back)

Design Architecture

Functional Highlights

• Implements MESI protocol for cache coherence.
• Supports silent and debug simulation modes.
• Provides detailed statistics, including cache hit/miss ratios and MESI state transitions.

Testing Strategies

• Validates read and write operations.
• Tests Pseudo-LRU functionality for efficient replacement.
• Evaluates MESI FSM transitions for different cache scenarios.

Testing MESI protocol

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This project was undertaken as part of the ECE585 course at Portland State University under the guidance of Prof. Mark G. Faust.