Author: Soham Kapur
Description: Implementation of a generalized Parallel Multiplier using Carry Save Adder with SystemVerilog and Xilinx Vivado.
Tools Used: SystemVerilog HDL, Xilinx Vivado
Concepts used: Parameterization, Parallel Multiplier, Carry Save Adder
Multiplier Schematic: 4x4 multiplier
Adder Row Schematic: Individual instance of Intermediate Product module
