OpenROAD-flow-scripts design configuration for a fully open-source hardware security module ASIC with IHP's open PDK.
RISC-V core based on VexRiscv, extended with masked AES as well as a big number multiplication unit. Eight 32KiB SRAM cells to hold firmware, stack, heap etc. Refer to the hardware/software repository for details.
To build the ASIC, set up OpenROAD-flow-scripts, clone this repository as <ORFS-Root>/flow/designs/ihp-sg13g2/hsm and run the build like any other ORFS design.
Signal pins on the east side of the chip are currently causing routing issues, thus the side is left empty.
Find the build taped out on 11/12/2023 in the releases.