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Vector extension simx without testcases #201

Closed
wants to merge 138 commits into from
Closed

Vector extension simx without testcases #201

wants to merge 138 commits into from

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MichaelJSr
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Massive thanks to Troibe for his amazing work on the vector extension!

This is a fork of his work that has been updated to be up-to-date with the master branch, as well as adding regression testing, a bit more debug logging, and a few other modifications.

This PR has the vector testcases removed due to their large size.

troibe added 30 commits January 11, 2024 20:21
@troibe
Introduce gitignores
ac1f8c3
@troibe
Add riscv-vector-tests
85dc5cd
@troibe
Add riscv-vector-tests to regression
7142223
@troibe
Allow execution of single vector tests
cd7a6a7
@troibe
Adjust gitignore to only cover simx binary
95d41e7
@troibe
Add support for vector registers
e3ea627
@troibe
Separate out vector execution
a8fd566
@troibe
Add support for vset(i)vl(i)
ef17a76
@troibe
Add support for vle and vse
35e1930
@troibe
Fix vadd.vi
7739e09
@troibe
Add more vector immidiate instructions
a33a3ff 
- vrsub.vi
- vand.vi
- vor.vi
- vxor.vi
- vsll.vi
- vsrl.vi
- vsra.vi
@troibe
Add support for vadd.vx
152c5cd
@troibe
Add unrecognised vector instruction warnings
ddbae52
@troibe
Add more vector scalar instructions
fb7f2cd 
- vsub.vx
- vrsub.vx
- vminu.vx
- vmin.vx
- vmaxu.vx
- vmax.vx
- vand.vx
- vor.vx
- vxor.vx
- vsll.vx
- vsrl.vx
- vsra.vx
- vmulhu.vx
- vmul.vx
- vmulh.vx
@troibe
Add initial vector vector instructions
4be8adb 
- vadd.vv
- vsub.vv
- vminu.vv
- vmin.vv
- vmaxu.vv
- vmax.vv
- vand.vv
- vor.vv
- vxor.vv
- vsll.vv
- vsrl.vv
- vsra.vv
@troibe
Add float vector vector instructions
6b897ee 
- vfmin.vv
- vfmax.vv
- vfcvt.f.x.v, vfcvt.x.f.v
- vfrec7.v, vfrsqrt7.v
@troibe
Add support for vmul, vmulh, vmulhu
548c896
@troibe
Add support for vwmul.vv
74d294e
@troibe
Refactor common functions
583f2b5
@troibe
Add initial reduction instructions
7288da4 
- vredsum.vs
- vredor.vs
@troibe
Add integer compare mask instructions
a4045da 
- vmseq.vv
- vmsne.vv
- vmsltu.vv
- vmslt.vv
- vmsleu.vv
- vmsle.vv
- vmsgtu.vv
- vmsgt.vv
@troibe
Add mask bits comparison instructions
1faabb1 
- vmandn.mm
- vmand.mm
- vmor.mm
- vmxor.mm
- vmorn.mm
- vmnand.mm
- vmnor.mm
- vmxnor.mm
@troibe
Add precompiled vector tests
e922917
@troibe
Switch to https for riscv-vector-tests submodule's submodules
77fb22c
@troibe
Fix test mode calling convenction for riscv-vector-tests
388b932
@troibe
Add support for X64
26e914d
@troibe
Only run supported test cases by default
0f79234
@troibe
Use upstream riscv-vector-tests as https is merged
bcfdee9
@troibe
Add vector test case documentation
1dd2c47
@troibe
Fix CSR issue for vset with X64
22f03a9
@MichaelJSr
updated riscv_test case for simx and rtlsim drivers
3334f53
@MichaelJSr
attempt to manually add recip7 and rsqrte7 for riscv-vector isa
df2ce0d 
fix an include

add f32_recip7 and include header in rvfloats
@MichaelJSr
modified includes
4cbed8e
@MichaelJSr
Update softfloat_ext.cpp
215623a 
Update softfloat_ext.cpp

Added softfloat_ext.cpp to Makefiles
@MichaelJSr
Added explicit fallthrough statements to remove warning
3db056d
@MichaelJSr
Added f16_classify, f32_classify, f64_classify
399fc6d
@MichaelJSr
Update rvfloats.cpp
81b80b9
@MichaelJSr
Added riscv-vector-tests to configure
98f7a10
@MichaelJSr
riscv-vector softfloat_ext modification
0e53e81 
Revert "Update softfloat_ext.cpp"

This reverts commit 215623a.
@MichaelJSr
Merge remote-tracking branch 'upstream/master' into riscv-vector-isa
1108e9c
@MichaelJSr
riscv-vector regression test changes
48b04f8 
vector isa regression test changes

vector isa regression test changes

riscv-vector include changes
@MichaelJSr
riscv-vector regression test changes
f8670a0
@MichaelJSr
vector test regression changes
18be708 
fixed syntax error
@MichaelJSr
riscv vector regression test edits
3406d74 
Update VX_csr_unit.sv

riscv vector regression test edits
@MichaelJSr
riscv vector test edits
8b2dea0 
Update VX_csr_unit.sv

Update VX_csr_unit.sv

Update VX_csr_unit.sv
@MichaelJSr
Merge remote-tracking branch 'origin/HEAD' into riscv-vector-isa
b47cbaa
@MichaelJSr
Removed vector extension testcases
4b3da9b
@troibe
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troibe commented Nov 3, 2024

Great, so Hyesoon wanted to upload the test cases on dropbox instead of GitHub releases.
Let's wait until that is done and integrate it in the test script then.

I think we generally want the fallback order to be:

  1. Copy locally generated testcases from the submodule if available
  2. Use existing testcases (from submodule or downloaded) if available
  3. Download testcases

I saw that you commented out the line for copying over the test cases.
Did that lead to issues for you? If yes let's try to resolve these...
The user should be able to regenerate the test cases themselves if they want to.

@MichaelJSr
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Sorry I did not have any issues with the line for copying over testcases, I will go ahead and uncomment it out. The fallback order makes sense, let me know if there are any other changes you would like me to make!

@MichaelJSr MichaelJSr force-pushed the riscv-vector-isa-simx branch from 5287dbc to 33f6110 Compare November 4, 2024 01:02
@MichaelJSr
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I implemented the fallback measures, I am going to close this pull request and open a new one with a clean history so that the vector test cases don't inflate the size of the git history.

@troibe
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troibe commented Nov 27, 2024

Ok great! Thanks for continuing to work on it.
Just mark me as a reviewer on the new one.

@MichaelJSr
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Thanks! I wanted to add you as a reviewer on the new pull request, but I don't have those permissions. Closing this PR!

@MichaelJSr MichaelJSr closed this Nov 27, 2024
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3 participants
@MichaelJSr @troibe @tinebp