bram reset fix

vortexgpgpu · Aug 3, 2024 · 9c5aee5 · 9c5aee5
1 parent c1b8ecf
commit 9c5aee5
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Showing 4 changed files with 10 additions and 2 deletions.
diff --git a/hw/rtl/cache/VX_cache_data.sv b/hw/rtl/cache/VX_cache_data.sv
@@ -91,9 +91,10 @@ module VX_cache_data #(
                 .SIZE  (`CS_LINES_PER_BANK)
             ) byteen_store (
                 .clk   (clk),
+                .reset (1'b0),
                 .read  (write || fill || flush),
                 .write (init || write || fill || flush),
-                `UNUSED_PIN (wren),
+                .wren  (1'b1),
                 .addr  (line_sel),
                 .wdata (bs_wdata),
                 .rdata (bs_rdata)
@@ -161,6 +162,7 @@ module VX_cache_data #(
         .RW_ASSERT (1)
     ) data_store (
         .clk   (clk),
+        .reset (1'b0),
         .read  (line_read),
         .write (line_write),
         .wren  (line_wren),

diff --git a/hw/rtl/cache/VX_cache_tags.sv b/hw/rtl/cache/VX_cache_tags.sv
@@ -130,9 +130,10 @@ module VX_cache_tags #(
             .RW_ASSERT (1)
         ) tag_store (
             .clk   (clk),
+            .reset (1'b0),
             .read  (line_read),
             .write (line_write),
-            `UNUSED_PIN (wren),
+            .wren  (1'b1),
             .addr  (line_sel),
             .wdata (line_wdata),
             .rdata (line_rdata)

diff --git a/hw/rtl/libs/VX_sp_ram.sv b/hw/rtl/libs/VX_sp_ram.sv
@@ -23,12 +23,14 @@ module VX_sp_ram #(
     parameter NO_RWCHECK  = 0,
     parameter RW_ASSERT   = 0,
     parameter LUTRAM      = 0,
+    parameter RESET_RAM   = 0,
     parameter INIT_ENABLE = 0,
     parameter INIT_FILE   = "",
     parameter [DATAW-1:0] INIT_VALUE = 0,
     parameter ADDRW       = `LOG2UP(SIZE)
 ) (
     input wire               clk,
+    input wire               reset,
     input wire               read,
     input wire               write,
     input wire [WRENW-1:0]   wren,
@@ -45,12 +47,14 @@ module VX_sp_ram #(
         .NO_RWCHECK (NO_RWCHECK),
         .RW_ASSERT (RW_ASSERT),
         .LUTRAM (LUTRAM),
+        .RESET_RAM (RESET_RAM),
         .INIT_ENABLE (INIT_ENABLE),
         .INIT_FILE (INIT_FILE),
         .INIT_VALUE (INIT_VALUE),
         .ADDRW (ADDRW)
     ) dp_ram (
         .clk   (clk),
+        .reset (reset),
         .read  (read),
         .write (write),
         .wren  (wren),

diff --git a/hw/rtl/mem/VX_local_mem.sv b/hw/rtl/mem/VX_local_mem.sv
@@ -166,6 +166,7 @@ module VX_local_mem import VX_gpu_pkg::*; #(
             .WRENW (WORD_SIZE)
         ) data_store (
             .clk   (clk),
+            .reset (1'b0),
             .read  (1'b1),
             .write (per_bank_req_valid[i] && per_bank_req_ready[i] && per_bank_req_rw[i]),
             .wren  (per_bank_req_byteen[i]),