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Fix some clippy warnings #29

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Fix some clippy warnings #29

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d614717
Fix some clippy warnings
usbalbin Dec 20, 2024
929ed66
fmt
usbalbin Dec 20, 2024
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27 changes: 13 additions & 14 deletions src/rcc.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -413,7 +413,7 @@ macro_rules! ppre_calculate {
.unwrap_or($hclk);

// Calculate suitable divider
let ($bits, $ppre) = match ($hclk + $pclk - 1) / $pclk
let ($bits, $ppre) = match $hclk.div_ceil($pclk)
{
0 => unreachable!(),
1 => (PPRE::Div1, 1 as u8),
Expand Down Expand Up @@ -617,19 +617,18 @@ impl Rcc {
let rcc_hclk = self.config.rcc_hclk.unwrap_or(sys_ck.raw());

// Estimate divisor
let (hpre_bits, hpre_div) =
match (sys_ck.raw() + rcc_hclk - 1) / rcc_hclk {
0 => unreachable!(),
1 => (HPRE::Div1, 1),
2 => (HPRE::Div2, 2),
3..=5 => (HPRE::Div4, 4),
6..=11 => (HPRE::Div8, 8),
12..=39 => (HPRE::Div16, 16),
40..=95 => (HPRE::Div64, 64),
96..=191 => (HPRE::Div128, 128),
192..=383 => (HPRE::Div256, 256),
_ => (HPRE::Div512, 512),
};
let (hpre_bits, hpre_div) = match sys_ck.raw().div_ceil(rcc_hclk) {
0 => unreachable!(),
1 => (HPRE::Div1, 1),
2 => (HPRE::Div2, 2),
3..=5 => (HPRE::Div4, 4),
6..=11 => (HPRE::Div8, 8),
12..=39 => (HPRE::Div16, 16),
40..=95 => (HPRE::Div64, 64),
96..=191 => (HPRE::Div128, 128),
192..=383 => (HPRE::Div256, 256),
_ => (HPRE::Div512, 512),
};

// Calculate real AHB clock
let rcc_hclk = sys_ck.raw() / hpre_div;
Expand Down
2 changes: 1 addition & 1 deletion src/rcc/mco.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,7 @@ macro_rules! calculate_prescaler {
// Running?
if let Some(freq) = self.frequency {
// Calculate prescaler
let prescaler = match (in_ck + freq - 1) / freq {
let prescaler = match in_ck.div_ceil(freq) {
0 => unreachable!(),
x @ 1..=15 => x,
_ => {
Expand Down
6 changes: 2 additions & 4 deletions src/rcc/pll.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -129,8 +129,7 @@ fn vco_output_divider_setup(
let vco_out_target = max_output * min_div;

let vco_out_target = if (vco_out_target / min_output) > PLL_OUT_DIV_MAX {
let f = ((vco_out_target / min_output) + PLL_OUT_DIV_MAX - 1)
/ PLL_OUT_DIV_MAX;
let f = (vco_out_target / min_output).div_ceil(PLL_OUT_DIV_MAX);
vco_out_target / f
} else {
vco_out_target
Expand All @@ -152,8 +151,7 @@ fn vco_output_divider_setup(

// Input divisor, resulting in a reference clock in the
// range 2 to 16 MHz.
let pll_x_m_min =
(pllsrc + range.input_range.end() - 1) / range.input_range.end();
let pll_x_m_min = pllsrc.div_ceil(*range.input_range.end());
let pll_x_m_max = (pllsrc / range.input_range.start()).min(PLL_M_MAX);

// Iterative search for the lowest m value that minimizes
Expand Down
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