rcc: Calculate PLL clocks and implement core clock configuration logic

[astapleton]

This implements the PLL and clock configuration logic for the processor using the RCC peripheral.

• The pll module is responsible for configuring the VCOs and setting up the PLL dividers for the desired frequency
• The freeze method in the rcc module does the heavy lifting for making sure that the processor clocks are configured in the desired manner

Note: This is largely copied from the implementation in stm32h7xx-hal, although it significantly refactors and modifies the PLL configuration in the pll module. This was mostly due to the differences in the register definitions used by the calculation and the fact that the H5 family (and especially the H503 MCU) is quite a bit simpler than the H7 family. I made significant changes to the the PLL configuration due to the stm32h7xx-hal crate being a bit bugged: it calculates values for Q and R outputs that are invalid for fractional PLL configurations.

[richardeoin]

Ideally there would be an assert! statements to check the values here

[richardeoin]

This is by necessity quite complex and error-prone logic, and at a first review it looks good! The two options for PllConfigStrategy cover most use cases and keeps it simple. Can you explain a little more about the bug you saw with Q and R outputs for fractional dividers? The Q and R divider values are calculated from the vco output frequency, which should be valid in either integer or fractional mode

[astapleton]

This is by necessity quite complex and error-prone logic, and at a first review it looks good! The two options for PllConfigStrategy cover most use cases and keeps it simple. Can you explain a little more about the bug you saw with Q and R outputs for fractional dividers? The Q and R divider values are calculated from the vco output frequency, which should be valid in either integer or fractional mode

Looking back at the patch I originally made to address the error I found, it looks like because the H7 VCO derivation chooses the maximum output frequency for the VCO (see here), it looks like if a high enough frequency is chosen for the system clock, which is then derived from PLL1, it's not possible to select frequencies in the low megahertz range on a different PLL (divider is >128).

For instance, the fractional-pll example in #15 would not work with the H7 logic: it fails calculating a divider for PLL2Q, after having chosen the max VCO output frequency of 836MHz and needing an integer divider of 135 to get to 6.144MHz. It might be that I introduced an error while adapting it for H5, so perhaps it does work fine on an actual H7.

It looks like the patch I made (last year, so my memory is a bit fuzzy) ended up becoming quite a bit more extensive than just addressing that, so the VCO setup here is quite a bit different than the H7 code.

[richardeoin]

the H7 VCO derivation chooses the maximum output frequency for the VCO (see here), it looks like if a high enough frequency is chosen for the system clock, which is then derived from PLL1, it's not possible to select frequencies in the low megahertz range on a different PLL (divider is >128).

Aha, I ignored the use case of PLL outputs with frequencies of the (max VCO frequency/128) or less. Nice that you've improved that.

Thanks for adding the tests.