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[(maybe?)DON'T MERGE] Update pac #102

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wants to merge 14 commits into from
4 changes: 2 additions & 2 deletions .github/workflows/ci.yml
Original file line number Diff line number Diff line change
Expand Up @@ -22,8 +22,8 @@ jobs:
- stm32g474
- stm32g483
- stm32g484
#- stm32g491 # Does not seem ready yet
#- stm32g4a1 # Does not seem ready yet
- stm32g491 # Does not seem ready yet
- stm32g4a1 # Does not seem ready yet
features:
- log-rtt,defmt
# TODO: -log-rtt # log-rtt without defmt, more combos?
Expand Down
3 changes: 2 additions & 1 deletion Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,8 @@ version = "0.0.2"

[dependencies]
nb = "0.1.1"
stm32g4 = "0.15.1"
#stm32g4 = { git = "https://github.com/stm32-rs/stm32-rs-nightlies" } #"0.15.1"
stm32g4 = { version = "0.17.0", package = "stm32g4-staging" }
paste = "1.0"
bitflags = "1.2"
vcell = "0.1"
Expand Down
2 changes: 1 addition & 1 deletion examples/flash_with_rtic.rs
Original file line number Diff line number Diff line change
Expand Up @@ -73,7 +73,7 @@ mod app {

unsafe {
let mut flash = &(*stm32g4xx_hal::stm32::FLASH::ptr());
flash.acr.modify(|_, w| {
flash.acr().modify(|_, w| {
w.latency().bits(0b1000) // 8 wait states
});
}
Expand Down
233 changes: 126 additions & 107 deletions src/adc.rs

Large diffs are not rendered by default.

4 changes: 2 additions & 2 deletions src/can.rs
Original file line number Diff line number Diff line change
Expand Up @@ -55,9 +55,9 @@ where
{
Self::enable(&rcc.rb);

if rcc.rb.ccipr.read().fdcansel().is_hse() {
if rcc.rb.ccipr().read().fdcansel().is_hse() {
// Select P clock as FDCAN clock source
rcc.rb.ccipr.modify(|_, w| {
rcc.rb.ccipr().modify(|_, w| {
// This is sound, as `FdCanClockSource` only contains valid values for this field.
unsafe {
w.fdcansel().bits(FdCanClockSource::PCLK as u8);
Expand Down
36 changes: 18 additions & 18 deletions src/comparator.rs
Original file line number Diff line number Diff line change
Expand Up @@ -55,26 +55,26 @@ impl EnabledState for Enabled {}
impl EnabledState for Locked {}

macro_rules! impl_comp {
($($t:ident: $reg_t:ident, $reg:ident,)+) => {$(
($($t:ident: $reg:ident,)+) => {$(
pub struct $t {
_rb: PhantomData<()>,
}

impl $t {
pub fn csr(&self) -> &$crate::stm32::comp::$reg_t {
pub fn csr(&self) -> &$crate::stm32::comp::CCSR {
// SAFETY: The COMP1 type is only constructed with logical ownership of
// these registers.
&unsafe { &*COMP::ptr() }.$reg
&unsafe { &*COMP::ptr() }.$reg()
}
}
)+};
}

impl_comp! {
COMP1: C1CSR, c1csr,
COMP2: C2CSR, c2csr,
COMP3: C3CSR, c3csr,
COMP4: C4CSR, c4csr,
COMP1: c1csr,
COMP2: c2csr,
COMP3: c3csr,
COMP4: c4csr,
}
#[cfg(any(
feature = "stm32g473",
Expand All @@ -83,9 +83,9 @@ impl_comp! {
feature = "stm32g484"
))]
impl_comp! {
COMP5: C5CSR, c5csr,
COMP6: C6CSR, c6csr,
COMP7: C7CSR, c7csr,
COMP5: c5csr,
COMP6: c6csr,
COMP7: c7csr,
}

// TODO: Split COMP in PAC
Expand Down Expand Up @@ -162,13 +162,13 @@ macro_rules! positive_input_pin {
($COMP:ident, $pin_0:ident, $pin_1:ident) => {
impl PositiveInput<$COMP> for &$pin_0<Analog> {
fn setup(&self, comp: &$COMP) {
comp.csr().modify(|_, w| w.inpsel().bit(false))
comp.csr().modify(|_, w| w.inpsel().bit(false));
}
}

impl PositiveInput<$COMP> for &$pin_1<Analog> {
fn setup(&self, comp: &$COMP) {
comp.csr().modify(|_, w| w.inpsel().bit(true))
comp.csr().modify(|_, w| w.inpsel().bit(true));
}
}
};
Expand Down Expand Up @@ -213,7 +213,7 @@ macro_rules! negative_input_pin_helper {
}

fn setup(&self, comp: &$COMP) {
comp.csr().modify(|_, w| unsafe { w.inmsel().bits($bits) })
comp.csr().modify(|_, w| unsafe { w.inmsel().bits($bits) });
}
}
};
Expand Down Expand Up @@ -268,7 +268,7 @@ macro_rules! refint_input {

fn setup(&self, comp: &$COMP) {
comp.csr()
.modify(|_, w| unsafe { w.inmsel().bits(*self as u8) })
.modify(|_, w| unsafe { w.inmsel().bits(*self as u8) });
}
}
)+};
Expand All @@ -294,7 +294,7 @@ macro_rules! dac_input_helper {
}

fn setup(&self, comp: &$COMP) {
comp.csr().modify(|_, w| unsafe { w.inmsel().bits($bits) })
comp.csr().modify(|_, w| unsafe { w.inmsel().bits($bits) });
}
}
};
Expand Down Expand Up @@ -541,11 +541,11 @@ type Comparators = (COMP1, COMP2, COMP3, COMP4, COMP5, COMP6, COMP7);
/// Enables the comparator peripheral, and splits the [`COMP`] into independent [`COMP1`] and [`COMP2`]
pub fn split(_comp: COMP, rcc: &mut Rcc) -> Comparators {
// Enable COMP, SYSCFG, VREFBUF clocks
rcc.rb.apb2enr.modify(|_, w| w.syscfgen().set_bit());
rcc.rb.apb2enr().modify(|_, w| w.syscfgen().set_bit());

// Reset COMP, SYSCFG, VREFBUF
rcc.rb.apb2rstr.modify(|_, w| w.syscfgrst().set_bit());
rcc.rb.apb2rstr.modify(|_, w| w.syscfgrst().clear_bit());
rcc.rb.apb2rstr().modify(|_, w| w.syscfgrst().set_bit());
rcc.rb.apb2rstr().modify(|_, w| w.syscfgrst().clear_bit());

(
COMP1 { _rb: PhantomData },
Expand Down
38 changes: 19 additions & 19 deletions src/dac.rs
Original file line number Diff line number Diff line change
Expand Up @@ -179,7 +179,7 @@ macro_rules! dac_helper {
$trim:ident,
$mode:ident,
$dhrx:ident,
$dac_dor:ident,
$dor:ident,
$daccxdhr:ident,
$wave:ident,
$mamp:ident,
Expand All @@ -193,8 +193,8 @@ macro_rules! dac_helper {
pub fn enable(self) -> $CX<MODE_BITS, Enabled> {
let dac = unsafe { &(*<$DAC>::ptr()) };

dac.dac_mcr.modify(|_, w| unsafe { w.$mode().bits(MODE_BITS) });
dac.dac_cr.modify(|_, w| w.$en().set_bit());
dac.mcr().modify(|_, w| unsafe { w.$mode().bits(MODE_BITS) });
dac.cr().modify(|_, w| w.$en().set_bit());

$CX {
_enabled: PhantomData,
Expand All @@ -204,8 +204,8 @@ macro_rules! dac_helper {
pub fn enable_generator(self, config: GeneratorConfig) -> $CX<MODE_BITS, WaveGenerator> {
let dac = unsafe { &(*<$DAC>::ptr()) };

dac.dac_mcr.modify(|_, w| unsafe { w.$mode().bits(MODE_BITS) });
dac.dac_cr.modify(|_, w| unsafe {
dac.mcr().modify(|_, w| unsafe { w.$mode().bits(MODE_BITS) });
dac.cr().modify(|_, w| unsafe {
w.$wave().bits(config.mode);
w.$ten().set_bit();
w.$mamp().bits(config.amp);
Expand Down Expand Up @@ -235,19 +235,19 @@ macro_rules! dac_helper {
T: DelayUs<u32>,
{
let dac = unsafe { &(*<$DAC>::ptr()) };
dac.dac_cr.modify(|_, w| w.$en().clear_bit());
dac.dac_mcr.modify(|_, w| unsafe { w.$mode().bits(0) });
dac.dac_cr.modify(|_, w| w.$cen().set_bit());
dac.cr().modify(|_, w| w.$en().clear_bit());
dac.mcr().modify(|_, w| unsafe { w.$mode().bits(0) });
dac.cr().modify(|_, w| w.$cen().set_bit());
let mut trim = 0;
while true {
dac.dac_ccr.modify(|_, w| unsafe { w.$trim().bits(trim) });
dac.ccr().modify(|_, w| unsafe { w.$trim().bits(trim) });
delay.delay_us(64_u32);
if dac.dac_sr.read().$cal_flag().bit() {
if dac.sr().read().$cal_flag().bit() {
break;
}
trim += 1;
}
dac.dac_cr.modify(|_, w| w.$cen().clear_bit());
dac.cr().modify(|_, w| w.$cen().clear_bit());

$CX {
_enabled: PhantomData,
Expand All @@ -257,7 +257,7 @@ macro_rules! dac_helper {
/// Disable the DAC channel
pub fn disable(self) -> $CX<MODE_BITS, Disabled> {
let dac = unsafe { &(*<$DAC>::ptr()) };
dac.dac_cr.modify(|_, w| unsafe {
dac.cr().modify(|_, w| unsafe {
w.$en().clear_bit().$wave().bits(0).$ten().clear_bit()
});

Expand All @@ -272,20 +272,20 @@ macro_rules! dac_helper {
impl<const MODE_BITS: u8, ED> DacOut<u16> for $CX<MODE_BITS, ED> {
fn set_value(&mut self, val: u16) {
let dac = unsafe { &(*<$DAC>::ptr()) };
dac.$dhrx.write(|w| unsafe { w.bits(val as u32) });
dac.$dhrx().write(|w| unsafe { w.bits(val as u32) });
}

fn get_value(&mut self) -> u16 {
let dac = unsafe { &(*<$DAC>::ptr()) };
dac.$dac_dor.read().bits() as u16
dac.$dor().read().bits() as u16
}
}

/// Wave generator state implementation
impl<const MODE_BITS: u8> $CX<MODE_BITS, WaveGenerator> {
pub fn trigger(&mut self) {
let dac = unsafe { &(*<$DAC>::ptr()) };
dac.dac_swtrgr.write(|w| { w.$swtrig().set_bit() });
dac.swtrgr().write(|w| { w.$swtrig().set_bit() });
}
}
)+
Expand All @@ -300,8 +300,8 @@ macro_rules! dac {
cal_flag1,
otrim1,
mode1,
dac_dhr12r1,
dac_dor1,
dhr12r1,
dor1,
dacc1dhr,
wave1,
mamp1,
Expand All @@ -314,8 +314,8 @@ macro_rules! dac {
cal_flag2,
otrim2,
mode2,
dac_dhr12r2,
dac_dor2,
dhr12r2,
dor2,
dacc2dhr,
wave2,
mamp2,
Expand Down
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