Fix g070

Cargo.toml

@@ -21,7 +21,8 @@ nb = "1.0.0"
 fugit = "0.3.5"
 
 [dependencies.stm32g0]
-version = "0.14.0"
+# version = "0.15.1"
+git = "https://github.com/stm32-rs/stm32-rs-nightlies"
 features = ["rt"]
 
 [dependencies.bare-metal]

src/analog/adc.rs

@@ -362,7 +362,7 @@ where
             .modify(|_, w| unsafe { w.smp1().bits(self.sample_time as u8) });
 
         self.rb
-            .chselr() // set activ channel acording chapter 15.12.9 (ADC_CFGR1; CHSELRMOD=0)
+            .chselr0() // set active channel according chapter 15.12.9 (ADC_CFGR1; CHSELRMOD=0)
             .modify(|_, w| unsafe { w.chsel().bits(1 << PIN::channel()) });
     }
 }
@@ -415,7 +415,7 @@ where
             .modify(|_, w| unsafe { w.smp1().bits(self.sample_time as u8) });
 
         self.rb
-            .chselr()
+            .chselr0()
             .modify(|_, w| unsafe { w.chsel().bits(1 << PIN::channel()) });
 
         self.rb.isr.modify(|_, w| w.eos().set_bit());

src/dmamux.rs

@@ -185,13 +185,13 @@ macro_rules! dma_mux {
 #[cfg(any(feature = "stm32g070", feature = "stm32g071", feature = "stm32g081"))]
 dma_mux!(
     channels: {
-        C0: (ch0, dmamux_c0cr),
-        C1: (ch1, dmamux_c1cr),
-        C2: (ch2, dmamux_c2cr),
-        C3: (ch3, dmamux_c3cr),
-        C4: (ch4, dmamux_c4cr),
-        C5: (ch5, dmamux_c5cr),
-        C6: (ch6, dmamux_c6cr),
+        C0: (ch0, c0cr),
+        C1: (ch1, c1cr),
+        C2: (ch2, c2cr),
+        C3: (ch3, c3cr),
+        C4: (ch4, c4cr),
+        C5: (ch5, c5cr),
+        C6: (ch6, c6cr),
     },
 );
 

src/i2c/blocking.rs

@@ -186,8 +186,14 @@ macro_rules! i2c {
                 });
 
                 if config.slave_address_1 > 0 {
+                    let addr = if config.address_11bits {
+                        config.slave_address_1
+                    } else {
+                        config.slave_address_1 << 1
+                    };
+
                     i2c.oar1.write(|w| unsafe {
-                        w.oa1_7_1().bits(config.slave_address_1 as u8)
+                        w.oa1().bits(addr)
                         .oa1mode().bit(config.address_11bits)
                         .oa1en().set_bit()
                     });

src/spi.rs

@@ -186,7 +186,7 @@ macro_rules! spi {
                         .set_bit()
                         .rxonly()
                         .clear_bit()
-                        .dff()
+                        .crcl()
                         .clear_bit()
                         .bidimode()
                         .clear_bit()

src/timer/pwm.rs

@@ -271,7 +271,7 @@ pwm_advanced_hal! {
 
 #[cfg(any(feature = "stm32g070"))]
 pwm_advanced_hal! {
-    TIM15: (Channel1, cc1e: cc1ne, ccmr1_output, oc1pe, oc1m1, ccr1, moe),
+    TIM15: (Channel1, cc1e: cc1ne, ccmr1_output, oc1pe, oc1m, ccr1, moe),
 }
 
 #[cfg(any(feature = "stm32g071", feature = "stm32g081"))]