Code

RISC-V 64 support for RVM#1

Code

Open

gjz010 wants to merge 11 commits intorcore-os:masterrcore-os/RVM:masterfrom rcore-riscv-hypervisor-dev:mainrcore-riscv-hypervisor-dev/RVM:mainCopy head branch name to clipboard

+1,733-37

Commits

Commits on Mar 6, 2021

• Starting riscv.

  gjz010

  committed
  024d95b

Commits on May 4, 2021

• RISCV64 support.

  gjz010

  committed
  25cf94e

• Merge branch 'master' of https://github.com/rcore-os/RVM into main

  gjz010

  committed
  19d345e

• Workflow fix.

  gjz010

  committed
  9d90a61

• workflow.

  gjz010

  committed
  94135e4

Commits on May 10, 2021

• full rvm riscv support.

  gjz010

  committed
  fa31039

Commits on May 11, 2021

• bug fix: store ctx when vm migrate between CPUs.

  gjz010

  committed
  5cde71c

Commits on May 13, 2021

• downgrade x86_64 crate version to fit into rCore toolchain.

  gjz010

  committed
  5ccac8b

Commits on May 17, 2021

• bump rust-toolchain version and change allocation interface

  gjz010

  committed
  c84e30d

• add alignment for ffi

  gjz010

  committed
  7f216ef

• downgrade rust version and move vcpu.rs out

  gjz010

  committed
  2867e78