test: Fix and add IP testbenches missing from CI (#95)

* hw: Fix syntax in IP testbench compile scripts * hw: Canonicalize SSR verification, add to CI * hw: Fix `reqrsp_to_axi_tb` and underlying issue in `reqrsp_test` * gitlab-ci: Preliminarily add `reqrsp_interface` CI * hw: Also fix and enable `tb_axi_to_reqrsp`
pulp-platform · Jun 19, 2024 · 44ca8c4 · 44ca8c4
1 parent dc4a6a6
commit 44ca8c4
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Showing 11 changed files with 36 additions and 40 deletions.
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
@@ -58,9 +58,6 @@ snitch-cluster-sw-banshee:
 # - snitch_ipu
 # - snitch_dma
 # - snitch
-# Currently failing IP tests/scripts:
-# - reqrsp_interface
-# - snitch_ssr
 snitch-ip-tests:
   needs: []
   parallel:
@@ -69,6 +66,8 @@ snitch-ip-tests:
           - mem_interface
           - snitch_cluster
           - tcdm_interface
+          - snitch_ssr
+          - reqrsp_interface
   script:
     - cd hw/$IP
     - ./util/compile.sh

diff --git a/hw/reqrsp_interface/src/reqrsp_test.sv b/hw/reqrsp_interface/src/reqrsp_test.sv
@@ -27,7 +27,7 @@ package reqrsp_test;
       amo inside {
         AMOSwap, AMOAdd, AMOAnd,
         AMOOr, AMOXor, AMOMax,
-        AMOMaxu, AMOMin, AMOMinu, AMOSC} -> write == 1;
+        AMOMaxu, AMOMin, AMOMinu, AMOLR, AMOSC} -> write == 0;
     }
 
     // Reduce the amount of atomics.
@@ -36,7 +36,7 @@ package reqrsp_test;
       is_amo -> amo inside {
         AMOSwap, AMOAdd, AMOAnd,
         AMOOr, AMOXor, AMOMax,
-        AMOMaxu, AMOMin, AMOMinu
+        AMOMaxu, AMOMin, AMOMinu, AMOLR, AMOSC
       };
     }
 

diff --git a/hw/reqrsp_interface/test/axi_to_reqrsp_tb.sv b/hw/reqrsp_interface/test/axi_to_reqrsp_tb.sv
@@ -136,7 +136,7 @@ module axi_to_reqrsp_tb import reqrsp_pkg::*; #(
       reqrsp_monitor.rsp_mbx.get(rsp);
 
       // Check that we have seen the appropriate transactions on the inputs.
-      if (req.write) begin
+      if (req.write | is_amo(req.amo) | (req.amo == AMOSC)) begin
         axi_monitor.aw_mbx.peek(ax);
         axi_monitor.w_mbx.get(w);
         // Invert bits as this is signalled as a clear condition on AXI.
@@ -149,7 +149,7 @@ module axi_to_reqrsp_tb import reqrsp_pkg::*; #(
           else $error("[Write Strb] Expected `%h` got `%h`", w.w_strb, req.strb);
         assert(req.data == w.w_data)
           else $error("[Write Data] Expected `%h` got `%h`", w.w_data, req.data);
-        assert(req.write == 1);
+        assert(req.write == (req.amo == AMONone));
         assert (
           req.addr ==
             axi_pkg::beat_addr(ax.ax_addr, ax.ax_size, ax.ax_len, ax.ax_burst, id_cnt_write)

diff --git a/hw/reqrsp_interface/test/reqrsp_to_axi_tb.sv b/hw/reqrsp_interface/test/reqrsp_to_axi_tb.sv
@@ -135,8 +135,8 @@ module reqrsp_to_axi_tb import reqrsp_pkg::*; #(
       reqrsp_monitor.req_mbx.get(req);
       // check fields match
       // Writes and atomics.
-      // For each write the reqrsp bus we want to see a `aw` beat.
-      if (req.write) begin
+      // For each "AXI" write (i.e. incl. ATOPs) on the reqrsp bus we want to see a `aw` beat.
+      if (req.write | is_amo(req.amo) | (req.amo == AMOSC)) begin
         axi_monitor.aw_mbx.get(ax);
         axi_monitor.w_mbx.get(w);
 

diff --git a/hw/reqrsp_interface/util/compile.sh b/hw/reqrsp_interface/util/compile.sh
@@ -10,7 +10,7 @@ set -e
 
 [ ! -z "$VSIM" ] || VSIM=vsim
 
-$(BENDER) script vsim -t test \
+$BENDER script vsim -t test \
     --vlog-arg="-svinputport=compat" \
     --vlog-arg="-override_timescale 1ns/1ps" \
     --vlog-arg="-suppress 2583" \

diff --git a/hw/snitch_ssr/test/tb_simple_ssr.sv b/hw/snitch_ssr/test/tb_simple_ssr.sv
@@ -14,7 +14,7 @@ module tb_simple_ssr;
   localparam int unsigned NumLoops      = 4;
 
   // Test data parameters
-  localparam string       DataFile = "../test/tb_simple_ssr.hex";
+  localparam string       DataFile = "./test/tb_simple_ssr.hex";
   localparam int unsigned ValBase   = 'h0;
   localparam int unsigned IdxBase   = 'h2000;
   localparam int unsigned IdxStride = 'h800;  // Stride of index arrays of different sizes

diff --git a/hw/snitch_ssr/test/tb_simple_ssr_streamer.sv b/hw/snitch_ssr/test/tb_simple_ssr_streamer.sv
@@ -16,7 +16,7 @@ module tb_simple_ssr_streamer;
   localparam int unsigned WPorts    = 1;
 
   // Test data parameters
-  localparam string       DataFile = "../test/tb_simple_ssr_streamer.hex";
+  localparam string       DataFile = "./test/tb_simple_ssr_streamer.hex";
   localparam int unsigned ValBase   = 'h0;
   localparam int unsigned IdxBase   = 'h2000;
   localparam int unsigned IdxStride = 'h800;  // Stride of index arrays of different sizes

diff --git a/hw/snitch_ssr/util/compile.sh b/hw/snitch_ssr/util/compile.sh
@@ -10,7 +10,7 @@ set -e
 
 [ ! -z "$VSIM" ] || VSIM=vsim
 
-$(BENDER) script vsim -t test \
+$BENDER script vsim -t test \
     --vlog-arg="-svinputport=compat" \
     --vlog-arg="-override_timescale 1ns/1ps" \
     --vlog-arg="-suppress 2583" \

diff --git a/hw/snitch_ssr/util/run_vsim.sh b/hw/snitch_ssr/util/run_vsim.sh
@@ -0,0 +1,24 @@
+#!/bin/bash
+# Copyright 2024 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+#
+# Fabian Schuiki <[email protected]>
+# Andreas Kurth  <[email protected]>
+# Paul Scheffler <[email protected]>
+
+set -e
+ROOT=$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)
+
+[ ! -z "$VSIM" ] || VSIM=vsim
+
+call_vsim() {
+    # We treat accessing unwritten associative array (memory) locations as fatal
+    echo "log -r /*; run -all" | $QUESTA_SEPP $VSIM -c -coverage -voptargs='+acc +cover=sbecft' "$@" -fatal vsim-3829 | tee vsim.log 2>&1
+    (grep "SUCCESS" transcript)
+    (! grep -n "Fatal:" transcript)
+    (! grep -n "Error:" transcript)
+}
+
+call_vsim tb_simple_ssr
+call_vsim tb_simple_ssr_streamer
diff --git a/hw/snitch_ssr/util/start_simple_ssr.tcl b/hw/snitch_ssr/util/start_simple_ssr.tcl
diff --git a/hw/snitch_ssr/util/start_simple_ssr_streamer.tcl b/hw/snitch_ssr/util/start_simple_ssr_streamer.tcl