hw: Support multi-ID DMA (#144)

.gitlab-ci.yml

@@ -138,6 +138,14 @@ snitch-cluster-omega-vsim:
     - make bin/snitch_cluster.vsim
     - ./util/run.py sw/run.yaml --simulator vsim -j --run-dir runs/vsim
 
+# Test Multi-channel DMA
+snitch-cluster-mchan-vsim:
+  script:
+    - cd target/snitch_cluster
+    - make CFG_OVERRIDE=cfg/dma_mchan.hjson sw
+    - make bin/snitch_cluster.vsim
+    - ./util/run.py sw/dma_mchan.yaml --simulator vsim -j --run-dir runs/vsim
+
 ############
 # Non-free #
 ############

docs/rm/custom_instructions.md

@@ -90,6 +90,7 @@ DMCPY and DMCPYI initiate an asynchronous data movement with the parameters conf
 |--------------|-------------|-------------
 | config[0]    | decouple_rw | Decouple the handshakes of the read and write channels
 | config[1]    | enable_2d   | Enable two-dimensional transfer
+| config[4:2]  | channel_sel | Selects the DMA backend if a multi-channel DMA is used
 
 DMSTAT and DMSTATI place the selected *status* flag of the DMA into register *rd*. The following *status* flags are supported:
 

docs/schema/snitch_cluster.schema.json

@@ -134,6 +134,11 @@
             "description": "Id width of the wide AXI plug into the cluster.",
             "default": 1
         },
+        "dma_nr_channels": {
+            "type": "number",
+            "description": "The number of separate DMA channels to instantiate.",
+            "default": 1
+        },
         "user_width": {
             "type": "number",
             "description": "User width of the narrower AXI plug into the cluster.",

hw/snitch/src/snitch_pkg.sv

@@ -143,8 +143,8 @@ package snitch_pkg;
   } cluster_slave_dma_e;
 
   typedef enum int unsigned {
-    SDMAMst  = 32'd0,
-    SoCDMAIn = 32'd1,
+    SoCDMAIn = 32'd0,
+    SDMAMst  = 32'd1,
     ICache   = 32'd2
   } cluster_master_dma_e;
 

hw/snitch_cluster/src/snitch_cc.sv

@@ -23,6 +23,7 @@ module snitch_cc #(
   parameter int unsigned DMAUserWidth       = 0,
   parameter int unsigned DMANumAxInFlight   = 0,
   parameter int unsigned DMAReqFifoDepth    = 0,
+  parameter int unsigned DMANumChannels     = 0,
   /// Data port request type.
   parameter type         dreq_t             = logic,
   /// Data port response type.
@@ -114,33 +115,33 @@ module snitch_cc #(
   parameter type addr_t = logic [AddrWidth-1:0],
   parameter type data_t = logic [DataWidth-1:0]
 ) (
-  input  logic                       clk_i,
-  input  logic                       clk_d2_i,
-  input  logic                       rst_ni,
-  input  logic                       rst_int_ss_ni,
-  input  logic                       rst_fp_ss_ni,
-  input  logic [31:0]                hart_id_i,
-  input  snitch_pkg::interrupts_t    irq_i,
-  output hive_req_t                  hive_req_o,
-  input  hive_rsp_t                  hive_rsp_i,
+  input  logic                              clk_i,
+  input  logic                              clk_d2_i,
+  input  logic                              rst_ni,
+  input  logic                              rst_int_ss_ni,
+  input  logic                              rst_fp_ss_ni,
+  input  logic [31:0]                       hart_id_i,
+  input  snitch_pkg::interrupts_t           irq_i,
+  output hive_req_t                         hive_req_o,
+  input  hive_rsp_t                         hive_rsp_i,
   // Core data ports
-  output dreq_t                      data_req_o,
-  input  drsp_t                      data_rsp_i,
+  output dreq_t                             data_req_o,
+  input  drsp_t                             data_rsp_i,
   // TCDM Streamer Ports
-  output tcdm_req_t [TCDMPorts-1:0]  tcdm_req_o,
-  input  tcdm_rsp_t [TCDMPorts-1:0]  tcdm_rsp_i,
+  output tcdm_req_t [TCDMPorts-1:0]         tcdm_req_o,
+  input  tcdm_rsp_t [TCDMPorts-1:0]         tcdm_rsp_i,
   // Accelerator Offload port
   // DMA ports
-  output axi_req_t                   axi_dma_req_o,
-  input  axi_rsp_t                   axi_dma_res_i,
-  output logic                       axi_dma_busy_o,
-  output dma_events_t                axi_dma_events_o,
+  output axi_req_t    [DMANumChannels-1:0]  axi_dma_req_o,
+  input  axi_rsp_t    [DMANumChannels-1:0]  axi_dma_res_i,
+  output logic        [DMANumChannels-1:0]  axi_dma_busy_o,
+  output dma_events_t [DMANumChannels-1:0]  axi_dma_events_o,
   // Core event strobes
-  output snitch_pkg::core_events_t   core_events_o,
-  input  addr_t                      tcdm_addr_base_i,
+  output snitch_pkg::core_events_t          core_events_o,
+  input  addr_t                             tcdm_addr_base_i,
   // Cluster HW barrier
-  output logic                       barrier_o,
-  input  logic                       barrier_i
+  output logic                              barrier_o,
+  input  logic                              barrier_i
 );
 
   // FMA architecture is "merged" -> mulexp and macexp instructions are supported
@@ -385,6 +386,7 @@ module snitch_cc #(
       .AxiUserWidth (DMAUserWidth),
       .NumAxInFlight (DMANumAxInFlight),
       .DMAReqFifoDepth (DMAReqFifoDepth),
+      .NumChannels (DMANumChannels),
       .axi_ar_chan_t (axi_ar_chan_t),
       .axi_aw_chan_t (axi_aw_chan_t),
       .axi_req_t (axi_req_t),

hw/snitch_cluster/src/snitch_cluster.sv

@@ -31,7 +31,7 @@ module snitch_cluster
   parameter int unsigned WideDataWidth      = 512,
   /// AXI: id width in.
   parameter int unsigned NarrowIdWidthIn    = 2,
-  /// AXI: dma id with in *currently not available*
+  /// AXI: dma id width in.
   parameter int unsigned WideIdWidthIn      = 2,
   /// AXI: user width.
   parameter int unsigned NarrowUserWidth    = 1,
@@ -57,6 +57,8 @@ module snitch_cluster
   parameter int unsigned DMANumAxInFlight   = 3,
   /// Size of DMA request fifo.
   parameter int unsigned DMAReqFifoDepth    = 3,
+  /// Number of DMA channels.
+  parameter int unsigned DMANumChannels     = 1,
   /// Width of a single icache line.
   parameter int unsigned ICacheLineWidth [NrHives] = '{default: 0},
   /// Number of icache lines per set.
@@ -274,8 +276,8 @@ module snitch_cluster
   localparam int unsigned NrRuleIdcs = NrSlaves - 1;
   localparam int unsigned NrRules = (1 + AliasRegionEnable) * NrRuleIdcs;
 
-  // DMA, SoC Request, `n` instruction caches.
-  localparam int unsigned NrWideMasters = 2 + NrHives;
+  // SoC Request, DMA Channels, `n` instruction caches.
+  localparam int unsigned NrWideMasters = 1 + DMANumChannels + NrHives;
   localparam int unsigned WideIdWidthOut = $clog2(NrWideMasters) + WideIdWidthIn;
   // DMA X-BAR configuration
   localparam int unsigned NrWideSlaves = 3;
@@ -837,10 +839,10 @@ module snitch_cluster
     localparam int unsigned TcdmPorts = get_tcdm_ports(i);
     localparam int unsigned TcdmPortsOffs = get_tcdm_port_offs(i);
 
-    axi_mst_dma_req_t   axi_dma_req;
-    axi_mst_dma_resp_t  axi_dma_res;
+    axi_mst_dma_req_t   [DMANumChannels-1:0] axi_dma_req;
+    axi_mst_dma_resp_t  [DMANumChannels-1:0] axi_dma_res;
     interrupts_t irq;
-    dma_events_t        dma_core_events;
+    dma_events_t        [DMANumChannels-1:0] dma_core_events;
 
     sync #(.STAGES (2))
       i_sync_debug (.clk_i, .rst_ni, .serial_i (debug_req_i[i]), .serial_o (irq.debug));
@@ -863,6 +865,7 @@ module snitch_cluster
         .SnitchPMACfg (SnitchPMACfg),
         .DMANumAxInFlight (DMANumAxInFlight),
         .DMAReqFifoDepth (DMAReqFifoDepth),
+        .DMANumChannels (DMANumChannels),
         .dreq_t (reqrsp_req_t),
         .drsp_t (reqrsp_rsp_t),
         .tcdm_req_t (tcdm_req_t),
@@ -951,9 +954,11 @@ module snitch_cluster
         end
       end
       if (Xdma[i]) begin : gen_dma_connection
-        assign wide_axi_mst_req[SDMAMst] = axi_dma_req;
-        assign axi_dma_res = wide_axi_mst_rsp[SDMAMst];
-        assign dma_events = dma_core_events;
+        for (genvar j = 0; j < DMANumChannels; j++) begin : gen_dma_connection
+          assign wide_axi_mst_req[SDMAMst + j] = axi_dma_req[j];
+          assign axi_dma_res[j] = wide_axi_mst_rsp[SDMAMst + j];
+        end
+        assign dma_events = dma_core_events[0]; // Only first channel is tracked
       end
   end
 
@@ -1001,8 +1006,8 @@ module snitch_cluster
         .hive_rsp_o (hive_rsp_reshape),
         .ptw_data_req_o (ptw_req[i]),
         .ptw_data_rsp_i (ptw_rsp[i]),
-        .axi_req_o (wide_axi_mst_req[ICache+i]),
-        .axi_rsp_i (wide_axi_mst_rsp[ICache+i]),
+        .axi_req_o (wide_axi_mst_req[SDMAMst+DMANumChannels+i]),
+        .axi_rsp_i (wide_axi_mst_rsp[SDMAMst+DMANumChannels+i]),
         .icache_prefetch_enable_i (icache_prefetch_enable),
         .icache_events_o(icache_events_reshape),
         .sram_cfgs_i

hw/snitch_cluster/src/snitch_cluster_wrapper.sv.tpl

@@ -54,12 +54,12 @@ package ${cfg['pkg_name']};
   localparam int unsigned WideDataWidth = ${cfg['dma_data_width']};
 
   localparam int unsigned NarrowIdWidthIn = ${cfg['id_width_in']};
-  localparam int unsigned NrMasters = 3;
-  localparam int unsigned NarrowIdWidthOut = $clog2(NrMasters) + NarrowIdWidthIn;
+  localparam int unsigned NrNarrowMasters = 3;
+  localparam int unsigned NarrowIdWidthOut = $clog2(NrNarrowMasters) + NarrowIdWidthIn;
 
-  localparam int unsigned NrDmaMasters = 2 + ${cfg['nr_hives']};
+  localparam int unsigned NrWideMasters = 1 + ${cfg['dma_nr_channels']} + ${cfg['nr_hives']};
   localparam int unsigned WideIdWidthIn = ${cfg['dma_id_width_in']};
-  localparam int unsigned WideIdWidthOut = $clog2(NrDmaMasters) + WideIdWidthIn;
+  localparam int unsigned WideIdWidthOut = $clog2(NrWideMasters) + WideIdWidthIn;
 
   localparam int unsigned NarrowUserWidth = ${cfg['user_width']};
   localparam int unsigned WideUserWidth = ${cfg['dma_user_width']};
@@ -274,6 +274,7 @@ module ${cfg['name']}_wrapper (
     .NrBanks (${cfg['tcdm']['banks']}),
     .DMANumAxInFlight (${cfg['dma_axi_req_fifo_depth']}),
     .DMAReqFifoDepth (${cfg['dma_req_fifo_depth']}),
+    .DMANumChannels (${cfg['dma_nr_channels']}),
     .ICacheLineWidth (${cfg['pkg_name']}::ICacheLineWidth),
     .ICacheLineCount (${cfg['pkg_name']}::ICacheLineCount),
     .ICacheSets (${cfg['pkg_name']}::ICacheSets),