[Profile] Add interconnect profiling testbench support and python scr… #2131
ci.yml
on: push
tc-gcc
31s
riscv-isa-sim
12s
tc-llvm
55s
verilator
6m 2s
check-opcodes
6s
Matrix: build-apps-gcc
check-bootrom
10s
Matrix: build-apps-llvm
Matrix: verilator-model
Matrix: run-apps-halide
clean-up
7s
Matrix: clean-up-compile-runs