Merge branch 'master' into nw/axi_burst_unwrap

.ci/Memora.yml

@@ -83,6 +83,9 @@ artifacts:
       - src/axi_pkg.sv
       - src/axi_intf.sv
       - src/axi_test.sv
+      - src/axi_err_slv.sv
+      - src/axi_demux.sv
+      - src/axi_demux_simple.sv
       - src/axi_dw_downsizer.sv
       - src/axi_dw_converter.sv
       - test/tb_axi_dw_downsizer.sv
@@ -97,6 +100,9 @@ artifacts:
       - src/axi_pkg.sv
       - src/axi_intf.sv
       - src/axi_test.sv
+      - src/axi_err_slv.sv
+      - src/axi_demux.sv
+      - src/axi_demux_simple.sv
       - src/axi_dw_upsizer.sv
       - src/axi_dw_converter.sv
       - test/tb_axi_dw_upsizer.sv
@@ -125,6 +131,9 @@ artifacts:
       - src/axi_pkg.sv
       - src/axi_intf.sv
       - src/axi_test.sv
+      - src/axi_demux.sv
+      - src/axi_demux_simple.sv
+      - src/axi_err_slv.sv
       - src/axi_isolate.sv
       - test/tb_axi_isolate.sv
     outputs:
@@ -141,6 +150,7 @@ artifacts:
       - src/axi_id_prepend.sv
       - src/axi_id_remap.sv
       - src/axi_demux.sv
+      - src/axi_demux_simple.sv
       - src/axi_serializer.sv
       - src/axi_mux.sv
       - src/axi_id_serialize.sv
@@ -294,6 +304,7 @@ artifacts:
       - src/axi_intf.sv
       - src/axi_test.sv
       - src/axi_demux.sv
+      - src/axi_demux_simple.sv
       - src/axi_to_detailed_mem.sv
       - src/axi_to_mem.sv
       - src/axi_to_mem_banked.sv
@@ -310,8 +321,11 @@ artifacts:
       - src/axi_intf.sv
       - src/axi_test.sv
       - src/axi_demux.sv
+      - src/axi_demux_simple.sv
       - src/axi_err_slv.sv
       - src/axi_mux.sv
+      - src/axi_multicut.sv
+      - src/axi_xbar_unmuxed.sv
       - src/axi_xbar.sv
       - test/tb_axi_xbar.sv
     outputs:

Bender.yml

@@ -19,8 +19,8 @@ package:
     - "Florian Zaruba <[email protected]>"
 
 dependencies:
-  common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.31.1 }
-  common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.3 }
+  common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.37.0 }
+  common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.4 }
   tech_cells_generic:  { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.2 }
 
 export_include_dirs:
@@ -80,14 +80,18 @@ sources:
   - src/axi_multicut.sv
   - src/axi_to_axi_lite.sv
   - src/axi_to_mem.sv
+  - src/axi_zero_mem.sv
   # Level 4
+  - src/axi_interleaved_xbar.sv
   - src/axi_iw_converter.sv
   - src/axi_lite_xbar.sv
-  - src/axi_xbar.sv
+  - src/axi_xbar_unmuxed.sv
   - src/axi_to_mem_banked.sv
   - src/axi_to_mem_interleaved.sv
   - src/axi_to_mem_split.sv
   # Level 5
+  - src/axi_xbar.sv
+  # Level 6
   - src/axi_xp.sv
 
   - target: synth_test

CHANGELOG.md

@@ -7,6 +7,76 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 
 ## Unreleased
 
+## 0.39.6 - 2024-12-04
+### Added
+- Support connectivity in `axi_intercon_gen`. #351
+- Add `iomsb` function to avoid underflow in array lengths to `axi_pkg`. #355
+
+### Fixed
+- Make the case statements in `axi_dw_upsizer` unique. Add default cases to prevent simulator warnings. #348
+- Fix write channel assertions in `axi_rw_split`. #357
+- Tie unused `demux` port in pass-through termination in `axi_isolate`. #359
+
+### Changed
+- Improve VCS and Verilator support treewide. #358
+- Update `common_verification` to `v0.2.4` to include Verilator fixes.
+
+## 0.39.5 - 2024-10-24
+
+### Fixed
+- Disabled the interface variant of `axi_xbar_unmuxed` for VCS, as VCS does not support multi-dimensional arrays of interfaces yet.
+
+### Changed
+- `axi_id_serialize`: Revert #342 to fix boot problems of CVA6 in Cheshire.
+
+## 0.39.4 - 2024-07-25 (Yanked 2024-10-23)
+### Added
+- `axi_sim_mem`: Increase number of request ports, add multiport interface variant.
+- `axi_bus_compare`: Optionally consider AXI `size` field to only compare used data.
+- `AXI_BUS_DV`: Add property checking that bursts do not cross 4KiB page boundaries.
+- Add `axi_xbar_unmuxed`: Partial crossbar with unmultiplexed mst_ports.
+
+### Fixed
+- `axi_bus_compare`: Fix mismatch detection.
+- `axi_to_detailed_mem`: Only respond with `exokay` if `lock` was set on the request.
+  Bump `common_cells` for `mem_to_banks` fix.
+- `axi_dw_downsizer`: Fix `i_forward_b_beats_queue` underflow.
+- `axi_atop_filter`: Add reset state to internal FSM to avoid simulation bug in XSIM.
+- `axi_test`: Ensure random requests do not cross 4KiB page boundaries.
+
+### Changed
+- `axi_id_serializer`: Change internal design (and behavior) for simpler code, less hardware, and
+  less stalling.
+
+`v0.39.4` is fully **backward-compatible** to `v0.39.3`.
+
+## 0.39.3 - 2024-05-08
+### Added
+- `axi_sim_mem`: Allow response data for uninitialized region to have configurable defined value.
+- `axi_test`: add `clear_memory_regions` to `axi_rand_master`.
+- `axi_test`: Add `add_traffic_shaping_with_size` to `axi_rand_master` to allow for traffic shaping
+  with a custom size.
+
+### Changed
+- `axi_pkg`: Adjust `LatencyMode` parameter of `xbar_cfg_t` to bit vector from `xbar_pipeline_e`
+  enum to allow custom configurations.
+
+`v0.39.3` is fully **backward-compatible** to `v0.39.2`.
+
+## 0.39.2 - 2024-03-13
+
+### Added
+- `axi_interleaved_xbar`: An experimental crossbar extension interleaving memory transfers over #334
+  subordinate devices. ***Use at your own risk***.
+- `axi_zero_mem`: Implementing *\dev\zero* function for AXI. #334
+
+### Fixed
+- `axi_to_detailed_mem`: VCS crashed on default parameters 0, changed them to 1 #334
+- `axi_to_mem`: Add missing testmode pins #327
+- `axi_sim_mem`: Fix byte calculation in R and W forks #331
+
+`v0.39.2` is fully **backward-compatible** to `v0.39.1`.
+
 ## 0.39.1 - 2023-09-05
 
 ### Added

README.md

@@ -38,6 +38,7 @@ In addition to the documents linked in the following table, we are setting up [d
 | [`axi_id_prepend`](src/axi_id_prepend.sv)               | This module prepends/strips the MSB from the AXI IDs.                                                |                                  |
 | [`axi_id_remap`](src/axi_id_remap.sv)                   | Remap AXI IDs from wide IDs at the slave port to narrower IDs at the master port.                    | [Doc][doc.axi_id_remap]          |
 | [`axi_id_serialize`](src/axi_id_serialize.sv)           | Reduce AXI IDs by serializing transactions when necessary.                                           | [Doc][doc.axi_id_serialize]      |
+| [`axi_interleaved_xbar`](src/axi_interleaved_xbar.sv)   | Interleaved version of the crossbar. This module is experimental; use at your own risk.              |                                  |
 | [`axi_intf`](src/axi_intf.sv)                           | This file defines the interfaces we support.                                                         |                                  |
 | [`axi_isolate`](src/axi_isolate.sv)                     | A module that can isolate downstream slaves from receiving new AXI4 transactions.                    |                                  |
 | [`axi_iw_converter`](src/axi_iw_converter.sv)           | Convert between any two AXI ID widths.                                                               | [Doc][doc.axi_iw_converter]      |
@@ -67,7 +68,9 @@ In addition to the documents linked in the following table, we are setting up [d
 | [`axi_to_axi_lite`](src/axi_to_axi_lite.sv)             | AXI4 to AXI4-Lite protocol converter.                                                                |                                  |
 | [`axi_to_mem`](src/axi_to_mem.sv)                       | AXI4 to memory protocol (req, gnt, rvalid) converter. Additional banked, interleaved, split variant. |                                  |
 | [`axi_xbar`](src/axi_xbar.sv)                           | Fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports.               | [Doc](doc/axi_xbar.md)           |
+| [`axi_xbar_unmuxed`](src/axi_xbar_unmuxed.sv)           | Demux side of fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports. | [Doc](doc/axi_xbar.md)           |
 | [`axi_xp`](src/axi_xp.sv)                               | AXI Crosspoint (XP) with homomorphous slave and master ports.                                        |                                  |
+| [`axi_zero_mem`](src/axi_zero_mem.sv)                   | AXI-attached /dev/zero. All reads will be zero, writes are absorbed.                                 |                                  |
 
 ## Synthesizable Verification Modules
 

VERSION

@@ -1 +1 @@
-0.39.1
+0.39.6

axi.core

@@ -1,6 +1,6 @@
 CAPI=2:
 
-name : pulp-platform.org::axi:0.39.1
+name : pulp-platform.org::axi:0.39.6
 
 filesets:
   rtl:
@@ -60,10 +60,12 @@ filesets:
       - src/axi_multicut.sv
       - src/axi_to_axi_lite.sv
       - src/axi_to_mem.sv
+      - src/axi_zero_mem.sv
       # Level 4
+      - src/axi_interleaved_xbar.sv
       - src/axi_iw_converter.sv
       - src/axi_lite_xbar.sv
-      - src/axi_xbar.sv
+      - src/axi_xbar_unmuxed.sv
       - src/axi_to_mem_banked.sv
       - src/axi_to_mem_interleaved.sv
       - src/axi_to_mem_split.sv
@@ -72,6 +74,8 @@ filesets:
       - src/axi_sim_mem.sv
       - src/axi_test.sv
       # Level 5
+      - src/axi_xbar.sv
+      # Level 6
       - src/axi_xp.sv
     file_type : systemVerilogSource
     depend :
@@ -106,7 +110,7 @@ filesets:
       - test/tb_axi_xbar.sv
     file_type : systemVerilogSource
     depend :
-      - ">=pulp-platform.org::common_verification:0.2.3"
+      - ">=pulp-platform.org::common_verification:0.2.4"
 
 generators:
   axi_intercon_gen:
@@ -134,11 +138,15 @@ generators:
 
                    offset (int): Base address for the slave
                    size   (int): Size of the allocated memory map for the slave
+                   slaves (list): List of device ports that this host is
+                                  connected to. A missing or empty list means
+                                  connection to all devices.
 
       Example usage:
         The following config will generate an interconnect wrapper to which two
         AXI4 master interfaces (dma and ibus) with different id widths are
         connected, and connects downstream to three AXI4 slaves (rom, gpio, ram)
+        The ibus port is only allowed to access the rom and ram ports.
 
         soc_intercon:
           generator: axi_intercon_gen
@@ -148,6 +156,7 @@ generators:
                 id_width : 1
               ibus:
                 id_width : 2
+                slaves: [ram, rom]
             slaves:
               ram:
                 offset : 0

ips_list.yml

@@ -1,9 +1,9 @@
 common_cells:
-    commit: v1.31.1
+    commit: v1.37.0
     group: pulp-platform
 
 common_verification:
-    commit: v0.2.3
+    commit: v0.2.4
     group: pulp-platform
 
 tech_cells_generic:

scripts/axi_intercon_gen.py

@@ -200,13 +200,12 @@ def load_dict(self, d):
         for key, value in d.items():
             if key == 'slaves':
                 # Handled in file loading, ignore here
-                continue
-            if key == 'id_width':
+                self.slaves = value
+            elif key == 'id_width':
                 self.idw = value
             elif key == 'read_only':
                 self.read_only = value
             else:
-                print(key)
                 raise UnknownPropertyError(
                     "Unknown property '%s' in master section '%s'" % (
                     key, self.name))
@@ -276,7 +275,7 @@ def construct_mapping(loader, node):
             print("Found slave " + k)
             self.slaves.append(Slave(k,v))
 
-        self.output_file = config.get('output_file', 'axi_intercon.v')
+        self.output_file = config.get('output_file', 'axi_intercon.sv')
         self.atop = config.get('atop', False)
 
     def _dump(self):
@@ -349,6 +348,7 @@ def write(self):
     MaxSlvTrans:        6,
     FallThrough:        1'b0,
     LatencyMode:        axi_pkg::CUT_ALL_AX,
+    PipelineStages:     0,
     AxiIdWidthSlvPorts: AxiIdWidthMasters,
     AxiIdUsedSlvPorts:  AxiIdUsed,
     UniqueIds:          1'b0,
@@ -403,14 +403,26 @@ def write(self):
         raw += "   mst_req_t  [{}:0] slaves_req;\n".format(ns-1)
         raw += "   mst_resp_t [{}:0] slaves_resp;\n".format(ns-1)
 
-        ns = len(self.slaves)
+        raw += f"\n  localparam bit [{nm-1}:0][{ns-1}:0] connectivity = " + '{\n   {'
+        connmap = []
+        for master in reversed(self.masters):
+            connstr = f"{ns}'b"
+            if master.slaves:
+                for slave in reversed(self.slaves):
+                    connstr += '1' if slave.name in master.slaves else '0'
+            else:
+                connstr += '1'*ns
+            connmap.append(connstr)
+        raw += "},\n   {".join(connmap)
+        raw += "}};\n"
 
         raw += assigns(w, max_idw, self.masters, self.slaves)
 
         self.verilog_writer.raw = raw
         parameters = [
             Parameter('Cfg'          , 'xbar_cfg' ),
             Parameter('ATOPs'        , "1'b"+str(int(self.atop))),
+            Parameter('Connectivity' , 'connectivity'),
             Parameter('slv_aw_chan_t', 'aw_chan_mst_t'),
             Parameter('mst_aw_chan_t', 'aw_chan_slv_t'),
             Parameter('w_chan_t'     , 'w_chan_t'     ),
@@ -439,14 +451,15 @@ def write(self):
                                           _template_ports))
 
         self.verilog_writer.write(file)
-        self.template_writer.write(file+'h')
+        template_file = file.split('.')[0]+'.vh'
+        self.template_writer.write(template_file)
 
         core_file = self.vlnv.split(':')[2]+'.core'
         vlnv = self.vlnv
         with open(core_file, 'w') as f:
             f.write('CAPI=2:\n')
             files = [{file     : {'file_type' : 'systemVerilogSource'}},
-                     {file+'h' : {'is_include_file' : True,
+                     {template_file : {'is_include_file' : True,
                                   'file_type' : 'verilogSource'}}
             ]
             coredata = {'name' : vlnv,

scripts/run_vsim.sh

@@ -49,6 +49,14 @@ exec_test() {
             call_vsim tb_$1
             ;;
         axi_dw_downsizer)
+            call_vsim tb_axi_dw_downsizer \
+                    -gTbAxiSlvPortDataWidth=32 \
+                    -gTbAxiMstPortDataWidth=16 \
+                    -gTbInitialBStallCycles=100000 -t 1ps
+            call_vsim tb_axi_dw_downsizer \
+                    -gTbAxiSlvPortDataWidth=32 \
+                    -gTbAxiMstPortDataWidth=16 \
+                    -gTbInitialRStallCycles=100000 -t 1ps
             for AxiSlvPortDataWidth in 8 16 32 64 128 256 512 1024; do
                 for (( AxiMstPortDataWidth = 8; \
                         AxiMstPortDataWidth < $AxiSlvPortDataWidth; \