Reverse Engineering libbl602_wifi

.github/workflows/action-libbl602_wifi.yml

@@ -0,0 +1,20 @@
+name: Compile libbl602_wifi
+on: [push]
+jobs:
+  build:
+    runs-on: ubuntu-latest
+    steps:
+    - uses: actions/checkout@v2
+    - name: Set up Clang
+      uses: egor-tensin/setup-clang@v1
+      with:
+        version: latest
+        platform: x64
+    - name: Build libbl602_wifi
+      run: mkdir build && cd build && cmake -DUSE_CLANG=ON .. && make -j && cd ..
+    - name: Archive artifacts
+      uses: actions/upload-artifact@v2
+      with:
+        name: libbl602_wifi
+        path: build/src/bl602_wifi/libbl602_wifi.a
+

.gitignore

@@ -305,3 +305,6 @@ tags
 [._]*.un~
 
 # End of https://www.toptal.com/developers/gitignore/api/emacs,vim,pycharm+all,python
+/build*
+.vscode/
+*.cache

CMakeLists.txt

@@ -0,0 +1,44 @@
+cmake_minimum_required(VERSION 3.14.0)
+set(CMAKE_SYSTEM_NAME Generic)
+
+set(CMAKE_USER_MAKE_RULES_OVERRIDE cmake/c_extension.cmake)
+set(CMAKE_C_OUTPUT_EXTENSION_REPLACE 1) # This is critical to producing the correct object files name for bl602 linker script
+
+set(CMAKE_SYSTEM_PROCESSOR riscv)
+SET(CMAKE_CROSSCOMPILING 1)
+set(CMAKE_TRY_COMPILE_TARGET_TYPE "STATIC_LIBRARY")
+
+option(USE_CLANG "build application with clang" OFF)
+if(USE_CLANG)
+    set(CMAKE_C_COMPILER clang)
+    set(CMAKE_C_COMPILER_TARGET "riscv32-unknown-elf")
+    set(CMAKE_CXX_COMPILER clang++)
+    set(CMAKE_CXX_COMPILER_TARGET "riscv32-unknown-elf")
+    set(CMAKE_TOOLCHAIN_PREFIX llvm-)
+    set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -fcommon ") # generate correct section for uninitialized data
+else()
+    set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -fstrict-volatile-bitfields") 
+    # this makes GCC access peripherals memory with respect to word align
+    # rather than byte align (e.g. sb/lb)
+endif()
+
+set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -std=c++11 -march=rv32imfc -mabi=ilp32f -DARCH_RISCV")
+set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -std=c11 -march=rv32imfc -mabi=ilp32f -DARCH_RISCV")
+
+project(bl602_re VERSION 0.1.0)
+
+include_directories(./src/include)
+include(cmake/add_module.cmake)
+
+option(FREERTOS_RAM "build with freertos ram" ON)
+if (FREERTOS_RAM)
+    include_directories(./components/bl602/freertos_riscv_ram/config)
+    include_directories(./components/bl602/freertos_riscv_ram/portable/GCC/RISC-V)
+    include_directories(./components/bl602/freertos_riscv_ram/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions)
+else()
+    include_directories(./components/bl602/freertos_riscv/config)
+    include_directories(./components/bl602/freertos_riscv/portable/GCC/RISC-V)
+    include_directories(./components/bl602/freertos_riscv/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions)
+endif()
+
+add_subdirectory(./src/bl602_wifi)

README.adoc

@@ -45,6 +45,17 @@ Whatever you do, do not insert proprietary `Copyright (C) RivieraWaves` code in
 RivieraWaves code is known to be easily available on GitHub with simple searches, but avoid looking at it, unless you wish to forfeit your right to directly contribute code here.
 ====
 
+== BL602 wifi
+I'm working on the reverse engineering of the bl602 wifi. 
+
+The source code is located in `src/` instead of `components/**`.
+
+Using `cmake` to build the wifi module and it will automatically add other components
+from the original `libbl602_wifi.a` and create a new one.
+
+This should generate a usable `libbl602_wifi.a` to link against other bl602 components.
+But, I'm still working on this and it hasn't been tested yet. 
+
 == Resources
 
 * https://github.com/pine64/bl602-docs[Pine64 SDK fork's documentation], if you figure something out that's documentation-worthy, please update that documentation.

alios/reg_intc.h

@@ -0,0 +1,237 @@
+/**
+ * @file reg_intc.h
+ * @brief Definitions of the INTC HW block registers and register access functions.
+ *
+ * @defgroup REG_INTC REG_INTC
+ * @ingroup REG
+ * @{
+ *
+ * @brief Definitions of the INTC HW block registers and register access functions.
+ */
+#ifndef _REG_INTC_H_
+#define _REG_INTC_H_
+
+#include "co_int.h"
+#include "_reg_intc.h"
+#include "compiler.h"
+#include "arch.h"
+#include "reg_access.h"
+
+/** @brief Number of registers in the REG_INTC peripheral.
+ */
+#define REG_INTC_COUNT 17
+
+/** @brief Decoding mask of the REG_INTC peripheral registers from the CPU point of view.
+ */
+#define REG_INTC_DECODING_MASK 0x0000007F
+
+/**
+ * @name IRQ_STATUS register definitions
+ *
+ * @{
+ */
+
+/// Address of the IRQ_STATUS register
+#define INTC_IRQ_STATUS_ADDR   0x10910000
+/// Offset of the IRQ_STATUS register from the base address
+#define INTC_IRQ_STATUS_OFFSET 0x00000000
+/// Index of the IRQ_STATUS register
+#define INTC_IRQ_STATUS_INDEX  0x00000000
+/// Reset value of the IRQ_STATUS register
+#define INTC_IRQ_STATUS_RESET  0x00000000
+/// Number of elements of the IRQ_STATUS register array
+#define INTC_IRQ_STATUS_COUNT  2
+
+/**
+ * @brief Returns the current value of the IRQ_STATUS register.
+ * The IRQ_STATUS register will be read and its value returned.
+ * @param[in] reg_idx Index of the register
+ * @return The current value of the IRQ_STATUS register.
+ */
+__INLINE uint32_t intc_irq_status_get(int reg_idx)
+{
+    ASSERT_ERR(reg_idx <= 1);
+    return REG_PL_RD(INTC_IRQ_STATUS_ADDR + reg_idx * 4);
+}
+
+/// @}
+
+/**
+ * @name IRQ_RAW_STATUS register definitions
+ *
+ * @{
+ */
+
+/// Address of the IRQ_RAW_STATUS register
+#define INTC_IRQ_RAW_STATUS_ADDR   0x10910008
+/// Offset of the IRQ_RAW_STATUS register from the base address
+#define INTC_IRQ_RAW_STATUS_OFFSET 0x00000008
+/// Index of the IRQ_RAW_STATUS register
+#define INTC_IRQ_RAW_STATUS_INDEX  0x00000002
+/// Reset value of the IRQ_RAW_STATUS register
+#define INTC_IRQ_RAW_STATUS_RESET  0x00000000
+/// Number of elements of the IRQ_RAW_STATUS register array
+#define INTC_IRQ_RAW_STATUS_COUNT  2
+
+/**
+ * @brief Returns the current value of the IRQ_RAW_STATUS register.
+ * The IRQ_RAW_STATUS register will be read and its value returned.
+ * @param[in] reg_idx Index of the register
+ * @return The current value of the IRQ_RAW_STATUS register.
+ */
+__INLINE uint32_t intc_irq_raw_status_get(int reg_idx)
+{
+    ASSERT_ERR(reg_idx <= 1);
+    return REG_PL_RD(INTC_IRQ_RAW_STATUS_ADDR + reg_idx * 4);
+}
+
+/// @}
+
+/**
+ * @name IRQ_UNMASK_SET register definitions
+ *
+ * @{
+ */
+
+/// Address of the IRQ_UNMASK_SET register
+#define INTC_IRQ_UNMASK_SET_ADDR   0x10910010
+/// Offset of the IRQ_UNMASK_SET register from the base address
+#define INTC_IRQ_UNMASK_SET_OFFSET 0x00000010
+/// Index of the IRQ_UNMASK_SET register
+#define INTC_IRQ_UNMASK_SET_INDEX  0x00000004
+/// Reset value of the IRQ_UNMASK_SET register
+#define INTC_IRQ_UNMASK_SET_RESET  0x00000000
+/// Number of elements of the IRQ_UNMASK_SET register array
+#define INTC_IRQ_UNMASK_SET_COUNT  2
+
+/**
+ * @brief Returns the current value of the IRQ_UNMASK_SET register.
+ * The IRQ_UNMASK_SET register will be read and its value returned.
+ * @param[in] reg_idx Index of the register
+ * @return The current value of the IRQ_UNMASK_SET register.
+ */
+__INLINE uint32_t intc_irq_unmask_get(int reg_idx)
+{
+    ASSERT_ERR(reg_idx <= 1);
+    return REG_PL_RD(INTC_IRQ_UNMASK_SET_ADDR + reg_idx * 4);
+}
+
+/**
+ * @brief Sets the IRQ_UNMASK_SET register to a value.
+ * The IRQ_UNMASK_SET register will be written.
+ * @param[in] reg_idx Index of the register
+ * @param value - The value to write.
+ */
+__INLINE void intc_irq_unmask_set(int reg_idx, uint32_t value)
+{
+    ASSERT_ERR(reg_idx <= 1);
+    REG_PL_WR(INTC_IRQ_UNMASK_SET_ADDR + reg_idx * 4, value);
+}
+
+/// @}
+
+/**
+ * @name IRQ_UNMASK_CLEAR register definitions
+ *
+ * @{
+ */
+
+/// Address of the IRQ_UNMASK_CLEAR register
+#define INTC_IRQ_UNMASK_CLEAR_ADDR   0x10910018
+/// Offset of the IRQ_UNMASK_CLEAR register from the base address
+#define INTC_IRQ_UNMASK_CLEAR_OFFSET 0x00000018
+/// Index of the IRQ_UNMASK_CLEAR register
+#define INTC_IRQ_UNMASK_CLEAR_INDEX  0x00000006
+/// Reset value of the IRQ_UNMASK_CLEAR register
+#define INTC_IRQ_UNMASK_CLEAR_RESET  0x00000000
+/// Number of elements of the IRQ_UNMASK_CLEAR register array
+#define INTC_IRQ_UNMASK_CLEAR_COUNT  2
+
+/**
+ * @brief Sets the IRQ_UNMASK_CLEAR register to a value.
+ * The IRQ_UNMASK_CLEAR register will be written.
+ * @param[in] reg_idx Index of the register
+ * @param value - The value to write.
+ */
+__INLINE void intc_irq_unmask_clear(int reg_idx, uint32_t value)
+{
+    ASSERT_ERR(reg_idx <= 1);
+    REG_PL_WR(INTC_IRQ_UNMASK_CLEAR_ADDR + reg_idx * 4, value);
+}
+
+/// @}
+
+/**
+ * @name IRQ_POLARITY register definitions
+ *
+ * @{
+ */
+
+/// Address of the IRQ_POLARITY register
+#define INTC_IRQ_POLARITY_ADDR   0x10910020
+/// Offset of the IRQ_POLARITY register from the base address
+#define INTC_IRQ_POLARITY_OFFSET 0x00000020
+/// Index of the IRQ_POLARITY register
+#define INTC_IRQ_POLARITY_INDEX  0x00000008
+/// Reset value of the IRQ_POLARITY register
+#define INTC_IRQ_POLARITY_RESET  0x00000000
+/// Number of elements of the IRQ_POLARITY register array
+#define INTC_IRQ_POLARITY_COUNT  2
+
+/**
+ * @brief Returns the current value of the IRQ_POLARITY register.
+ * The IRQ_POLARITY register will be read and its value returned.
+ * @param[in] reg_idx Index of the register
+ * @return The current value of the IRQ_POLARITY register.
+ */
+__INLINE uint32_t intc_irq_polarity_get(int reg_idx)
+{
+    ASSERT_ERR(reg_idx <= 1);
+    return REG_PL_RD(INTC_IRQ_POLARITY_ADDR + reg_idx * 4);
+}
+
+/**
+ * @brief Sets the IRQ_POLARITY register to a value.
+ * The IRQ_POLARITY register will be written.
+ * @param[in] reg_idx Index of the register
+ * @param value - The value to write.
+ */
+__INLINE void intc_irq_polarity_set(int reg_idx, uint32_t value)
+{
+    ASSERT_ERR(reg_idx <= 1);
+    REG_PL_WR(INTC_IRQ_POLARITY_ADDR + reg_idx * 4, value);
+}
+
+/// @}
+
+/**
+ * @name IRQ_INDEX register definitions
+ *
+ * @{
+ */
+
+/// Address of the IRQ_INDEX register
+#define INTC_IRQ_INDEX_ADDR   0x10910040
+/// Offset of the IRQ_INDEX register from the base address
+#define INTC_IRQ_INDEX_OFFSET 0x00000040
+/// Index of the IRQ_INDEX register
+#define INTC_IRQ_INDEX_INDEX  0x00000010
+/// Reset value of the IRQ_INDEX register
+#define INTC_IRQ_INDEX_RESET  0x00000000
+
+/**
+ * @brief Returns the current value of the IRQ_INDEX register.
+ * The IRQ_INDEX register will be read and its value returned.
+ * @return The current value of the IRQ_INDEX register.
+ */
+__INLINE uint32_t intc_irq_index_get(void)
+{
+    return REG_PL_RD(INTC_IRQ_INDEX_ADDR);
+}
+
+/// @}
+
+
+#endif // _REG_INTC_H_
+
+/// @}

blobs/bz_phy.c

@@ -25,7 +25,5 @@ void bz_phy_reset(void)
   write_volatile_4(0x40002810,uVar1 & 0xfffffffe);
   uVar1 = read_volatile_4(0x40002810);
   write_volatile_4(0x40002810,uVar1 | 0x2);
-  uVar1 = read_volatile_4(0x40002cac);
-  write_volatile_4(0x40002cac,uVar1 & 0xffffffe0 | 0x4);
   return;
 }