gimlet-seq: Record why the power state changed

drv/cpu-seq-api/src/lib.rs

@@ -9,6 +9,7 @@
 use counters::Count;
 use derive_idol_err::IdolError;
 use userlib::{sys_send, FromPrimitive};
+use zerocopy::AsBytes;
 
 // Re-export PowerState for client convenience.
 pub use drv_cpu_power_state::PowerState;
@@ -31,6 +32,36 @@ pub enum SeqError {
     ServerRestarted,
 }
 
+#[derive(Copy, Clone, Debug, FromPrimitive, Eq, PartialEq, AsBytes, Count)]
+#[repr(u8)]
+pub enum StateChangeReason {
+    /// No reason was provided.
+    ///
+    /// This indicates a legacy caller of `Sequencer.set_state`, rather than
+    /// `Sequencer.set_state_with_reason`. All Hubris-internal callers should
+    /// use `set_state_with_reason`, so this variant generally indicates that
+    /// the `Sequencer.set_state` IPC is being called via Hiffy.
+    Other = 1,
+    /// The system has just received power, so the sequencer has booted the
+    /// host CPU.
+    InitialPowerOn,
+    /// A power state change was requested by the control plane.
+    ControlPlane,
+    /// The host CPU reset while in A0, so the system has powered off to clear
+    /// hidden core state.
+    CpuReset,
+    /// The host OS failed to boot, so the system has powered off.
+    HostBootFailure,
+    /// The host OS panicked.
+    HostPanic,
+    /// The host OS requested that the system power off without rebooting.
+    HostPowerOff,
+    /// The host OS requested that the system reboot.
+    HostReboot,
+    /// The system powered off because a component has overheated.
+    Overheat,
+}
+
 // On Gimlet, we have two banks of up to 8 DIMMs apiece. Export the "two banks"
 // bit of knowledge here so it can be used by gimlet-seq-server, spd, and
 // packrat, all of which want to know at compile-time how many banks there are.

drv/gimlet-seq-server/src/main.rs

@@ -17,7 +17,7 @@ use userlib::{
     sys_set_timer, task_slot, units, RecvMessage, TaskId, UnwrapLite,
 };
 
-use drv_cpu_seq_api::{PowerState, SeqError};
+use drv_cpu_seq_api::{PowerState, SeqError, StateChangeReason};
 use drv_hf_api as hf_api;
 use drv_i2c_api as i2c;
 use drv_ice40_spi_program as ice40;
@@ -90,7 +90,13 @@ enum Trace {
     RailsOn,
     UartEnabled,
     A0(u16),
-    SetState(PowerState, PowerState, u64),
+    SetState {
+        prev: PowerState,
+        next: PowerState,
+        #[count(children)]
+        why: StateChangeReason,
+        now: u64,
+    },
     UpdateState(#[count(children)] PowerState),
     ClockConfigWrite,
     ClockConfigSuccess,
@@ -482,7 +488,10 @@ impl<S: SpiServer + Clone> ServerImpl<S> {
 
         // Power on, unless suppressed by the `stay-in-a2` feature
         if !cfg!(feature = "stay-in-a2") {
-            _ = server.set_state_internal(PowerState::A0);
+            _ = server.set_state_internal(
+                PowerState::A0,
+                StateChangeReason::InitialPowerOn,
+            );
         }
 
         //
@@ -666,11 +675,17 @@ impl<S: SpiServer> ServerImpl<S> {
     fn set_state_internal(
         &mut self,
         state: PowerState,
+        why: StateChangeReason,
     ) -> Result<(), SeqError> {
         let sys = sys_api::Sys::from(SYS.get_task_id());
 
         let now = sys_get_timer().now;
-        ringbuf_entry!(Trace::SetState(self.state, state, now));
+        ringbuf_entry!(Trace::SetState {
+            prev: self.state,
+            next: state,
+            why,
+            now
+        });
 
         ringbuf_entry_v3p3_sys_a0_vout();
 
@@ -813,6 +828,7 @@ impl<S: SpiServer> ServerImpl<S> {
 
                 //
                 // Now wait for the end of Group C.
+
                 //
                 loop {
                     let mut status = [0u8];
@@ -1029,11 +1045,21 @@ impl<S: SpiServer> idl::InOrderSequencerImpl for ServerImpl<S> {
     }
 
     fn set_state(
+        &mut self,
+        msg: &RecvMessage,
+        state: PowerState,
+    ) -> Result<(), RequestError<SeqError>> {
+        self.set_state_with_reason(msg, state, StateChangeReason::Other)
+    }
+
+    fn set_state_with_reason(
         &mut self,
         _: &RecvMessage,
         state: PowerState,
+        reason: StateChangeReason,
     ) -> Result<(), RequestError<SeqError>> {
-        self.set_state_internal(state).map_err(RequestError::from)
+        self.set_state_internal(state, reason)
+            .map_err(RequestError::from)
     }
 
     fn send_hardware_nmi(
@@ -1403,7 +1429,7 @@ cfg_if::cfg_if! {
 }
 
 mod idl {
-    use super::SeqError;
+    use super::{SeqError, StateChangeReason};
 
     include!(concat!(env!("OUT_DIR"), "/server_stub.rs"));
 }

drv/grapefruit-seq-server/src/main.rs

@@ -7,7 +7,7 @@
 #![no_std]
 #![no_main]
 
-use drv_cpu_seq_api::PowerState;
+use drv_cpu_seq_api::{PowerState, StateChangeReason};
 use drv_spi_api::{SpiDevice, SpiServer};
 use drv_stm32xx_sys_api as sys_api;
 use idol_runtime::{NotificationHandler, RequestError};
@@ -29,6 +29,7 @@ enum Trace {
     ContinueBitstreamLoad(usize),
     WaitForDone,
     Programmed,
+
     #[count(skip)]
     None,
 }
@@ -282,9 +283,18 @@ impl<S: SpiServer + Clone> idl::InOrderSequencerImpl for ServerImpl<S> {
     }
 
     fn set_state(
+        &mut self,
+        msg: &RecvMessage,
+        state: PowerState,
+    ) -> Result<(), RequestError<drv_cpu_seq_api::SeqError>> {
+        self.set_state_with_reason(msg, state, StateChangeReason::Other)
+    }
+
+    fn set_state_with_reason(
         &mut self,
         _: &RecvMessage,
         state: PowerState,
+        _: StateChangeReason,
     ) -> Result<(), RequestError<drv_cpu_seq_api::SeqError>> {
         match (self.get_state_impl(), state) {
             (PowerState::A2, PowerState::A0)
@@ -327,7 +337,7 @@ impl<S: SpiServer> NotificationHandler for ServerImpl<S> {
 }
 
 mod idl {
-    use drv_cpu_seq_api::SeqError;
+    use drv_cpu_seq_api::{SeqError, StateChangeReason};
     include!(concat!(env!("OUT_DIR"), "/server_stub.rs"));
 }
 

drv/mock-gimlet-seq-server/src/main.rs

@@ -7,7 +7,7 @@
 #![no_std]
 #![no_main]
 
-use drv_cpu_seq_api::{PowerState, SeqError};
+use drv_cpu_seq_api::{PowerState, SeqError, StateChangeReason};
 use idol_runtime::{NotificationHandler, RequestError};
 use task_jefe_api::Jefe;
 use userlib::{FromPrimitive, RecvMessage, UnwrapLite};
@@ -55,9 +55,18 @@ impl idl::InOrderSequencerImpl for ServerImpl {
     }
 
     fn set_state(
+        &mut self,
+        msg: &RecvMessage,
+        state: PowerState,
+    ) -> Result<(), RequestError<SeqError>> {
+        self.set_state_with_reason(msg, state, StateChangeReason::Other)
+    }
+
+    fn set_state_with_reason(
         &mut self,
         _: &RecvMessage,
         state: PowerState,
+        _: StateChangeReason,
     ) -> Result<(), RequestError<SeqError>> {
         match (self.get_state_impl(), state) {
             (PowerState::A2, PowerState::A0)
@@ -99,7 +108,7 @@ impl NotificationHandler for ServerImpl {
 }
 
 mod idl {
-    use super::SeqError;
+    use super::{SeqError, StateChangeReason};
 
     include!(concat!(env!("OUT_DIR"), "/server_stub.rs"));
 }

idl/cpu-seq.idol

@@ -13,12 +13,29 @@ Interface(
             idempotent: true,
         ),
         "set_state": (
+            doc: "Set the power state without providing a reason (legacy).",
+            args: {
+                "state": (
+                    type: "drv_cpu_power_state::PowerState",
+                    recv: FromPrimitive("u8"),
+                ),
+            },
+            reply: Result(
+                ok: "()",
+                err: CLike("SeqError"),
+            ),
+        ),
+        "set_state_with_reason": (
             doc: "Set the power state",
             args: {
                 "state": (
                     type: "drv_cpu_power_state::PowerState",
                     recv: FromPrimitive("u8"),
-                )
+                ),
+                "reason": (
+                    type: "StateChangeReason",
+                    recv: FromPrimitive("u8"),
+                ),
             },
             reply: Result(
                 ok: "()",

task/control-plane-agent/src/mgs_compute_sled.rs

@@ -728,7 +728,10 @@ impl SpHandler for MgsHandler {
         };
 
         self.sequencer
-            .set_state(power_state)
+            .set_state_with_reason(
+                power_state,
+                drv_cpu_seq_api::StateChangeReason::ControlPlane,
+            )
             .map_err(|e| SpError::PowerStateError(e as u32))
     }