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don't have IPC methods call each other
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hawkw committed Dec 18, 2024
1 parent 1088947 commit 0939d49
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Showing 3 changed files with 40 additions and 31 deletions.
5 changes: 3 additions & 2 deletions drv/gimlet-seq-server/src/main.rs
Original file line number Diff line number Diff line change
Expand Up @@ -1046,10 +1046,11 @@ impl<S: SpiServer> idl::InOrderSequencerImpl for ServerImpl<S> {

fn set_state(
&mut self,
msg: &RecvMessage,
_: &RecvMessage,
state: PowerState,
) -> Result<(), RequestError<SeqError>> {
self.set_state_with_reason(msg, state, StateChangeReason::Other)
self.set_state_internal(state, reason)
.map_err(RequestError::from)
}

fn set_state_with_reason(
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35 changes: 19 additions & 16 deletions drv/grapefruit-seq-server/src/main.rs
Original file line number Diff line number Diff line change
Expand Up @@ -269,6 +269,17 @@ impl<S: SpiServer + Clone> ServerImpl<S> {
fn set_state_impl(&self, state: PowerState) {
self.jefe.set_state(state as u32);
}

fn validate_state_change(&self, state: PowerState) -> Result<(), SeqError> {
match (self.get_state_impl(), state) {
(PowerState::A2, PowerState::A0)
| (PowerState::A0, PowerState::A2)
| (PowerState::A0PlusHP, PowerState::A2)
| (PowerState::A0Thermtrip, PowerState::A2) => Ok(()),

_ => Err(SeqError::IllegalTransition),
}
}
}

// The `Sequencer` implementation for Grapefruit is copied from
Expand All @@ -286,29 +297,21 @@ impl<S: SpiServer + Clone> idl::InOrderSequencerImpl for ServerImpl<S> {
&mut self,
msg: &RecvMessage,
state: PowerState,
) -> Result<(), RequestError<drv_cpu_seq_api::SeqError>> {
self.set_state_with_reason(msg, state, StateChangeReason::Other)
) -> Result<(), RequestError<SeqError>> {
self.validate_state_change(state)?;
self.set_state_impl(state);
Ok(())
}

fn set_state_with_reason(
&mut self,
_: &RecvMessage,
state: PowerState,
_: StateChangeReason,
) -> Result<(), RequestError<drv_cpu_seq_api::SeqError>> {
match (self.get_state_impl(), state) {
(PowerState::A2, PowerState::A0)
| (PowerState::A0, PowerState::A2)
| (PowerState::A0PlusHP, PowerState::A2)
| (PowerState::A0Thermtrip, PowerState::A2) => {
self.set_state_impl(state);
Ok(())
}

_ => Err(RequestError::Runtime(
drv_cpu_seq_api::SeqError::IllegalTransition,
)),
}
) -> Result<(), RequestError<SeqError>> {
self.validate_state_change(state)?;
self.set_state_impl(state);
Ok(())
}

fn send_hardware_nmi(
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31 changes: 18 additions & 13 deletions drv/mock-gimlet-seq-server/src/main.rs
Original file line number Diff line number Diff line change
Expand Up @@ -44,6 +44,17 @@ impl ServerImpl {
fn set_state_impl(&self, state: PowerState) {
self.jefe.set_state(state as u32);
}

fn validate_state_change(&self, state: PowerState) -> Result<(), SeqError> {
match (self.get_state_impl(), state) {
(PowerState::A2, PowerState::A0)
| (PowerState::A0, PowerState::A2)
| (PowerState::A0PlusHP, PowerState::A2)
| (PowerState::A0Thermtrip, PowerState::A2) => Ok(()),

_ => Err(SeqError::IllegalTransition),
}
}
}

impl idl::InOrderSequencerImpl for ServerImpl {
Expand All @@ -56,10 +67,12 @@ impl idl::InOrderSequencerImpl for ServerImpl {

fn set_state(
&mut self,
msg: &RecvMessage,
_: &RecvMessage,
state: PowerState,
) -> Result<(), RequestError<SeqError>> {
self.set_state_with_reason(msg, state, StateChangeReason::Other)
self.validate_state_change(state)?;
self.set_state_impl(state);
Ok(())
}

fn set_state_with_reason(
Expand All @@ -68,17 +81,9 @@ impl idl::InOrderSequencerImpl for ServerImpl {
state: PowerState,
_: StateChangeReason,
) -> Result<(), RequestError<SeqError>> {
match (self.get_state_impl(), state) {
(PowerState::A2, PowerState::A0)
| (PowerState::A0, PowerState::A2)
| (PowerState::A0PlusHP, PowerState::A2)
| (PowerState::A0Thermtrip, PowerState::A2) => {
self.set_state_impl(state);
Ok(())
}

_ => Err(RequestError::Runtime(SeqError::IllegalTransition)),
}
self.validate_state_change(state)?;
self.set_state_impl(state);
Ok(())
}

fn send_hardware_nmi(
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