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    • ocra

      Public
      MRI console
      Python
      GNU General Public License v3.0
      2039224Updated Dec 23, 2024Dec 23, 2024
    • rust-hdl

      Public
      A framework for writing FPGA firmware using the Rust Programming Language
      Rust
      Other
      20000Updated Dec 8, 2024Dec 8, 2024
    • egui

      Public
      egui: an easy-to-use immediate mode GUI in Rust that runs on both web and native
      Rust
      Apache License 2.0
      1.6k000Updated Oct 16, 2023Oct 16, 2023
    • nifti-rs

      Public
      Rust implementation of the NIfTI-1 format
      Rust
      Apache License 2.0
      12000Updated Jun 6, 2023Jun 6, 2023
    • Enables tracing for pyo3-based embedded python applications using Python's logging module.
      Rust
      1000Updated Jun 1, 2023Jun 1, 2023
    • Yocto layer to provide support for common Zynq based FPGA boards used in the community
      BitBake
      MIT License
      0350Updated Apr 13, 2023Apr 13, 2023
    • The official FreeSurfer repository maintained by LCN
      C++
      Other
      250100Updated Mar 21, 2023Mar 21, 2023
    • The official Linux kernel from Xilinx
      C
      Other
      1.5k000Updated Nov 29, 2021Nov 29, 2021
    • ocra-pack

      Public
      A packaged 1.0 distribution of OCRA tools for easy use!
      MIT License
      0110Updated Mar 24, 2021Mar 24, 2021
    • Source files and published documents for the FEniCS tutorial.
      TeX
      303000Updated Feb 16, 2021Feb 16, 2021
    • Verilog AXI stream components for FPGA implementation
      Python
      MIT License
      230100Updated Oct 25, 2019Oct 25, 2019
    • Needed scripts to produce awesome coils
      MATLAB
      Other
      14200Updated Jul 3, 2019Jul 3, 2019
    • The official Xilinx u-boot repository
      C
      791000Updated Jun 28, 2019Jun 28, 2019
    • libuio

      Public
      UserspaceIO helper library
      C
      GNU Lesser General Public License v2.1
      28000Updated Jun 17, 2019Jun 17, 2019
    • OpenMRI Project Website
      0000Updated Mar 14, 2019Mar 14, 2019
    • LTE SDR cell scanner optimized to work with very low performance RF front ends (8bit A/D, 20dB noise figure)
      C++
      GNU Affero General Public License v3.0
      357000Updated Feb 26, 2019Feb 26, 2019
    • riffa

      Public
      The RIFFA development repository
      Verilog
      Other
      315000Updated Feb 4, 2019Feb 4, 2019
    • snickerdoodle Base Vivado Projects
      HTML
      4000Updated Jan 15, 2019Jan 15, 2019
    • A parameterizable Vivado HLS project (C/C++) that implements a master and slave AXI-Stream to AXI-Memory-Mapped data mover (AXI-S defaults to 8 bits and AXI-MM to 64 bits)
      VHDL
      6000Updated Aug 29, 2018Aug 29, 2018
    • Custom components for KiCAD
      3100Updated Jan 26, 2018Jan 26, 2018
    • lsuio

      Public
      lsuio -- utility to list UIO devices
      C
      3000Updated Jan 3, 2017Jan 3, 2017
    • SystemVerilog
      13000Updated Jul 28, 2016Jul 28, 2016
    • C
      10000Updated Jul 28, 2016Jul 28, 2016