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halt target state: halted target halted in ARM state due to debug-request, current mode: Supervisor cpsr: 0x20000193 pc: 0x80494c50 MMU: enabled, D-Cache: enabled, I-Cache: enabled ttbcr 0ttbr0 328f004attbr1 1000404a imx6.cpu.0 rev a, partnum c09, arch f, variant 2, implementor 41 number of cache level 1 imx6.cpu.0 cluster 0 core 0 multi core target state: halted target halted in ARM state due to debug-request, current mode: Supervisor cpsr: 0x200f0113 pc: 0x80081a10 MMU: enabled, D-Cache: enabled, I-Cache: enabled

# make sure l2x cache is configured. This configuration is SoC specific. TODO: for some reasons l2x is not configured from the script. cache l2x conf 0xa02000 16

cache l1 info D-Cache: linelen 32, associativity 4, nsets 255, cachesize 32 KBytes I-Cache: linelen 32, associativity 4, nsets 255, cachesize 32 KBytes

cache l2x info L2 unified cache Base Address 0xa02000, 16 ways

#lets play. Disable auto cache handling targets imx6.cpu.0 dap apsel 1 cache auto 0 targets imx6.cpu.1 cache auto 0 dap apsel 1

# first test, single core operation > targets imx6.cpu.1 > mdw 0x80494c50 0x80494c50: e1d430b0 > mww 0x80494c50 0x0 > mdw 0x80494c50 0x80494c50: 00000000 > cache l1 d inval 0x80494c50 > mdw 0x80494c50 0x80494c50: e1d430b0

> targets imx6.cpu.1 > mdw 0x80494c50 0x80494c50: e1d430b0 # initial data > mww 0x80494c50 0x0 > targets imx6.cpu.0 > mdw 0x80494c50 0x80494c50: 00000000 > cache l1 d inval 0x80494c50 > mdw 0x80494c50 0x80494c50: 00000000 > targets imx6.cpu.1 > mdw 0x80494c50 0x80494c50: 00000000 > cache l1 d inval 0x80494c50 # drop l1 data cache > mdw 0x80494c50 0x80494c50: 00000000 # hmm... too late, already in l2x cache > cache l2x inval 0x80494c50 # drop l2x cache 80494c50 : 10494c50 outer shareable secured outer: Write-Back, Write-Allocate inner: Write-Back, Write-Allocate > mdw 0x80494c50 0x80494c50: e1d430b0 # ha... the data is back.