fix README.md

README.md

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 # GHDL Verilator Interface (GVI)
 
-GVI generates glue code that allows to run Verilog modules inside of VHDL testbenches. Have a look at the examples to see how it can be used. In order to run the m-labs-lm32, serv, ibex, hazard3, picorv32_soc or wr-cores examples, git submodules have to be activated (`git submodule init; git submodule update;`)
+GVI generates glue code that allows to run Verilog modules inside of VHDL testbenches. Have a look at the examples to see how it can be used. In order to run the m-labs-lm32, serv, ibex, hazard3, toy_SoC or wr-cores examples, git submodules have to be activated (`git submodule init; git submodule update;`)
 
  - examples/vhd_v_counter: Run a Verilog implementation of a counter with a VHDL implementation of the same counter in the same testbench.
  - examples/two_modules: Two Verilog modules used at the same time. They may have multiple clock ports.