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1. RTL-to-GDSII-of-Floating-Point-Multiplier RTL-to-GDSII-of-Floating-Point-Multiplier Public

   Design of a multiplier architecture that operates upon IEEE 754 single precision floating point numbers

   Verilog

2. BIST-for-Carry-Select-Adder BIST-for-Carry-Select-Adder Public

   Design of BIST architecture for self testing and fault diagnosis of a Carry Select Adder

   Verilog

3. Design-of-SAR-ADC Design-of-SAR-ADC Public

   Repository related to my Final Year Project at NIT Andhra Pradesh which includes designing a SAR ADC for biomedical applications

4. 4BIT-PIPELINED-ADDER 4BIT-PIPELINED-ADDER Public

   Implementation of a 4 bit pipelined ripple carry adder as a part of coursework under PhD scholar Banala Harika