GitHub - leonardocbsr/CoreBassier: RISC processor done in verilog hdl for FPGA

leonardocbsr / CoreBassier Public

RISC processor done in verilog hdl for FPGA

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Name		Name	Last commit message	Last commit date
Latest commit History 8 Commits
.qsys_edit		.qsys_edit
ALU		ALU
ControlUnit		ControlUnit
DataMemory		DataMemory
FrequencyDivider		FrequencyDivider
IO		IO
InstructionsMemory		InstructionsMemory
LCD		LCD
PC		PC
RegistersBank		RegistersBank
Report		Report
db		db
incremental_db		incremental_db
output_files		output_files
simulation		simulation
CoreBassier.qpf		CoreBassier.qpf
CoreBassier.qsf		CoreBassier.qsf
Waveform.vwf		Waveform.vwf
bugs		bugs
cr_ie_info.json		cr_ie_info.json
frequencyDivisor.v.bak		frequencyDivisor.v.bak
main.qpf		main.qpf
main.qsf		main.qsf
main.qws		main.qws
main.v		main.v
main.v.bak		main.v.bak