Fix bug where unconnected array drivers may be omitted incorrectly (#496

)
intel · Jun 26, 2024 · 23bd6a5 · 23bd6a5
1 parent e465234
commit 23bd6a5
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Showing 4 changed files with 72 additions and 12 deletions.
diff --git a/lib/src/module.dart b/lib/src/module.dart
@@ -417,13 +417,27 @@ abstract class Module {
           !isInput(signal) &&
           !isInOut(signal) &&
           subModule == null) {
+        _addInternalSignal(signal);
+
         // handle expanding the search for arrays
-        if (signal.isArrayMember) {
+        if (signal.parentStructure != null) {
           await _traceInputForModuleContents(signal.parentStructure!,
               dontAddSignal: dontAddSignal);
+          await _traceOutputForModuleContents(signal.parentStructure!,
+              dontAddSignal: signal.isPort);
+        }
+        if (signal is LogicStructure) {
+          for (final elem in signal.elements) {
+            await _traceInputForModuleContents(elem,
+                dontAddSignal: dontAddSignal);
+            await _traceOutputForModuleContents(elem,
+                dontAddSignal: signal.isPort);
+          }
         }
 
-        _addInternalSignal(signal);
+        for (final srcConnection in signal.srcConnections) {
+          await _traceOutputForModuleContents(srcConnection);
+        }
       }
 
       if (!dontAddSignal && isInput(signal)) {
@@ -520,13 +534,24 @@ abstract class Module {
           !isOutput(signal) &&
           !isInOut(signal) &&
           subModule == null) {
+        _addInternalSignal(signal);
+
         // handle expanding the search for arrays
-        if (signal.isArrayMember) {
+        if (signal.parentStructure != null) {
           await _traceOutputForModuleContents(signal.parentStructure!,
               dontAddSignal: dontAddSignal);
+          await _traceInputForModuleContents(signal.parentStructure!,
+              dontAddSignal: signal.isPort);
+        }
+        if (signal is LogicStructure) {
+          for (final elem in signal.elements) {
+            await _traceOutputForModuleContents(elem,
+                dontAddSignal: dontAddSignal);
+            await _traceInputForModuleContents(elem,
+                dontAddSignal: signal.isPort);
+          }
         }
 
-        _addInternalSignal(signal);
         for (final dstConnection in signal.dstConnections) {
           await _traceInputForModuleContents(dstConnection);
         }
@@ -558,10 +583,6 @@ abstract class Module {
 
     _internalSignals.add(signal);
 
-    if (signal.isArrayMember) {
-      _addInternalSignal(signal.parentStructure!);
-    }
-
     // ignore: invalid_use_of_protected_member
     signal.parentModule = this;
   }
@@ -661,7 +682,7 @@ abstract class Module {
     )
       ..gets(x)
       // ignore: invalid_use_of_protected_member
-      ..parentModule = this;
+      ..setAllParentModule(this);
 
     _inputs[name] = inArr;
 
@@ -707,7 +728,7 @@ abstract class Module {
       naming: Naming.reserved,
     )
       // ignore: invalid_use_of_protected_member
-      ..parentModule = this;
+      ..setAllParentModule(this);
 
     _outputs[name] = outArr;
 
@@ -751,7 +772,7 @@ abstract class Module {
     )
       ..gets(x)
       // ignore: invalid_use_of_protected_member
-      ..parentModule = this;
+      ..setAllParentModule(this);
 
     _inOuts[name] = inOutArr;
 

diff --git a/lib/src/signals/logic.dart b/lib/src/signals/logic.dart
@@ -180,7 +180,7 @@ class Logic {
 
   /// Sets the value of [parentModule] to [newParentModule].
   ///
-  /// This should *only* be called by [Module.build()].  It is used to
+  /// This should *only* be called by [Module.build].  It is used to
   /// optimize search.
   @protected
   set parentModule(Module? newParentModule) {

diff --git a/lib/src/signals/logic_structure.dart b/lib/src/signals/logic_structure.dart
@@ -251,7 +251,17 @@ class LogicStructure implements Logic {
         'Should only set parent module once.');
 
     _parentModule = newParentModule;
+  }
+
+  /// Performs a recursive call of setting [parentModule] on all of [elements]
+  /// and their [elements] for any sub-[LogicStructure]s.
+  @protected
+  void setAllParentModule(Module? newParentModule) {
+    parentModule = newParentModule;
     for (final element in elements) {
+      if (element is LogicStructure) {
+        element.setAllParentModule(newParentModule);
+      }
       element.parentModule = newParentModule;
     }
   }

diff --git a/test/module_test.dart b/test/module_test.dart
@@ -89,6 +89,24 @@ class ArrayConcatMod extends Module {
   }
 }
 
+class UnconnectedArraySig extends Module {
+  UnconnectedArraySig(Logic a) : super(name: 'unconnected_array_sig') {
+    a = addInput('a', a);
+
+    final aArr = LogicArray([2], 1, name: 'a_arr');
+    aArr.elements[0] <= a;
+    aArr.elements[1] <= Logic(name: 'unconnected');
+
+    SubModWithArray(aArr);
+  }
+}
+
+class SubModWithArray extends Module {
+  SubModWithArray(LogicArray aArr) : super(name: 'sub_mod_with_array') {
+    aArr = addInputArray('a_arr', aArr, dimensions: aArr.dimensions);
+  }
+}
+
 void main() {
   test('tryInput, exists', () {
     final mod = ModuleWithMaybePorts(addIn: true);
@@ -140,4 +158,15 @@ void main() {
     final sv = mod.generateSynth();
     expect(sv, contains('assign a_concat[0] = t0;'));
   });
+
+  test('array unconnected input port found', () async {
+    final mod = UnconnectedArraySig(Logic());
+    await mod.build();
+
+    expect(mod.internalSignals.firstWhereOrNull((e) => e.name == 'unconnected'),
+        isNotNull);
+
+    final sv = mod.generateSynth();
+    expect(sv, contains('assign a_arr[1] = unconnected;'));
+  });
 }