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Feature request: VHDL/verilog export from command line #1372

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GenericNerdyUsername opened this issue Dec 25, 2024 · 0 comments
Open

Feature request: VHDL/verilog export from command line #1372

GenericNerdyUsername opened this issue Dec 25, 2024 · 0 comments

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@GenericNerdyUsername
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Pretty much the title, having a command line way (pg29 of the english docs) to generate HDL would make testing easier for me
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@GenericNerdyUsername