Skip to content

Commit

Permalink
Merge pull request #32 from firesim/dev
Browse files Browse the repository at this point in the history
FireSim 1.12 Release (Dev -> Master) Tracking PR
  • Loading branch information
davidbiancolin authored Jun 14, 2021
2 parents b4544da + 6cd1a8c commit e2a9752
Show file tree
Hide file tree
Showing 9 changed files with 77 additions and 10 deletions.
Original file line number Diff line number Diff line change
Expand Up @@ -147,6 +147,8 @@ set_msg_config -id {Timing 38-436} -suppress
# Promote the following critical warnings to errors to prevent AGFI generation
# Design not completely routed
set_msg_config -id {Route 35-1} -new_severity "ERROR"
# Route 35-535] Clock Net: <net> is not completely routed.
set_msg_config -id {Route 35-535} -new_severity "ERROR"

# Check that an email address has been set, else unset notify_via_sns

Expand Down Expand Up @@ -175,6 +177,10 @@ switch $strategy {
puts "EXPLORE strategy."
source $HDK_SHELL_DIR/build/scripts/strategy_EXPLORE.tcl
}
"NORETIMING" {
puts "NORETIMING strategy."
source $HDK_SHELL_DIR/build/scripts/strategy_NORETIMING.tcl
}
"TIMING" {
puts "TIMING strategy."
source $HDK_SHELL_DIR/build/scripts/strategy_TIMING.tcl
Expand Down Expand Up @@ -279,7 +285,7 @@ if {$implement} {
impl_step opt_design $TOP "-merge_equivalent_drivers -sweep"
}
}
report_utilization -hierarchical -file $CL_DIR/build/reports/${timestamp}.post_opt_utilization.rpt
report_utilization -hierarchical -hierarchical_percentages -file $CL_DIR/build/reports/${timestamp}.post_opt_utilization.rpt

########################
# CL Place
Expand Down Expand Up @@ -325,7 +331,7 @@ if {$implement} {
report_timing_summary -file $CL_DIR/build/reports/${timestamp}.SH_CL_final_timing_summary.rpt

# Report utilization
report_utilization -hierarchical -file $CL_DIR/build/reports/${timestamp}.SH_CL_utilization.rpt
report_utilization -hierarchical -hierarchical_percentages -file $CL_DIR/build/reports/${timestamp}.SH_CL_utilization.rpt

# This is what will deliver to AWS
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) - Writing final DCP to to_aws directory.";
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -117,7 +117,7 @@ puts "AWS FPGA: ([clock format [clock seconds] -format %T]) Start design synthes

update_compile_order -fileset sources_1
puts "\nRunning synth_design for $CL_MODULE $CL_DIR/build/scripts \[[clock format [clock seconds] -format {%a %b %d %H:%M:%S %Y}]\]"
eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS $VDEFINES -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive -retiming]
eval [concat synth_design -top $CL_MODULE -verilog_define XSDB_SLV_DIS $VDEFINES -part [DEVICE_TYPE] -mode out_of_context $synth_options -directive $synth_directive]

set failval [catch {exec grep "FAIL" failfast.csv}]
if { $failval==0 } {
Expand All @@ -128,6 +128,9 @@ if { $failval==0 } {
puts "AWS FPGA: ([clock format [clock seconds] -format %T]) writing post synth checkpoint.";
write_checkpoint -force $CL_DIR/build/checkpoints/${timestamp}.CL.post_synth.dcp

report_utilization -hierarchical -hierarchical_percentages -file $CL_DIR/build/reports/${timestamp}.post_synth_utilization.rpt
report_control_sets -verbose -file $CL_DIR/build/reports/${timestamp}.post_synth_control_sets.rpt

close_project
#Set param back to default value
set_param sta.enableAutoGenClkNamePersistence 1
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@
# Usage help
function usage
{
echo "usage: aws_build_dcp_from_cl.sh [ [-script <vivado_script>] | [-strategy BASIC | DEFAULT | EXPLORE | TIMING | CONGESTION] [-clock_recipe_a A0 | A1 | A2] [-clock_recipe_b B0 | B1 | B2 | B3 | B4 | B5] [-clock_recipe_c C0 | C1 | C2 | C3] [-uram_option 2 | 3 | 4] [-vdefine macro1,macro2,macro3,.....,macrox] -foreground] [-notify] | [-h] | [-H] | [-help] ]"
echo "usage: aws_build_dcp_from_cl.sh [ [-script <vivado_script>] | [-strategy BASIC | DEFAULT | EXPLORE | TIMING | NORETIMING | CONGESTION] [-clock_recipe_a A0 | A1 | A2] [-clock_recipe_b B0 | B1 | B2 | B3 | B4 | B5] [-clock_recipe_c C0 | C1 | C2 | C3] [-uram_option 2 | 3 | 4] [-vdefine macro1,macro2,macro3,.....,macrox] -foreground] [-notify] | [-h] | [-H] | [-help] ]"
echo " "
echo "By default the build is run in the background using nohup so that the"
echo "process will not be terminated if the terminal window is closed."
Expand Down Expand Up @@ -117,7 +117,7 @@ fi

# Check that strategy is valid
shopt -s extglob
if [[ $strategy != @(BASIC|DEFAULT|EXPLORE|TIMING|CONGESTION) ]]; then
if [[ $strategy != @(BASIC|DEFAULT|EXPLORE|TIMING|CONGESTION|NORETIMING) ]]; then
err_msg "$strategy isn't a valid strategy. Valid strategies are BASIC, DEFAULT, EXPLORE, TIMING and CONGESTION."
exit 1
fi
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@
source $HDK_SHELL_DIR/build/scripts/params.tcl
source $HDK_SHELL_DIR/build/scripts/uram_options.tcl

set synth_options "-keep_equivalent_registers $synth_uram_option"
set synth_options "-keep_equivalent_registers $synth_uram_option -retiming"
set synth_directive "default"

#Set psip to 1 to enable Physical Synthesis in Placer
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@
source $HDK_SHELL_DIR/build/scripts/params.tcl
source $HDK_SHELL_DIR/build/scripts/uram_options.tcl

set synth_options "-no_lc -shreg_min_size 10 -control_set_opt_threshold 16 $synth_uram_option"
set synth_options "-no_lc -shreg_min_size 10 -control_set_opt_threshold 16 $synth_uram_option -retiming"
set synth_directive "AlternateRoutability"

#Set psip to 1 to enable Physical Synthesis in Placer
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@
source $HDK_SHELL_DIR/build/scripts/params.tcl
source $HDK_SHELL_DIR/build/scripts/uram_options.tcl

set synth_options "-keep_equivalent_registers -flatten_hierarchy rebuilt $synth_uram_option"
set synth_options "-keep_equivalent_registers -flatten_hierarchy rebuilt $synth_uram_option -retiming"
set synth_directive "default"

#Set psip to 1 to enable Physical Synthesis in Placer
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@
source $HDK_SHELL_DIR/build/scripts/params.tcl
source $HDK_SHELL_DIR/build/scripts/uram_options.tcl

set synth_options "-keep_equivalent_registers -flatten_hierarchy rebuilt $synth_uram_option"
set synth_options "-keep_equivalent_registers -flatten_hierarchy rebuilt $synth_uram_option -retiming"
set synth_directive "default"

#Set psip to 1 to enable Physical Synthesis in Placer
Expand Down
58 changes: 58 additions & 0 deletions hdk/common/shell_v04261818/build/scripts/strategy_NORETIMING.tcl
Original file line number Diff line number Diff line change
@@ -0,0 +1,58 @@
# Amazon FPGA Hardware Development Kit
#
# Copyright 2016 Amazon.com, Inc. or its affiliates. All Rights Reserved.
#
# Licensed under the Amazon Software License (the "License"). You may not use
# this file except in compliance with the License. A copy of the License is
# located at
#
# http://aws.amazon.com/asl/
#
# or in the "license" file accompanying this file. This file is distributed on
# an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, express or
# implied. See the License for the specific language governing permissions and
# limitations under the License.

source $HDK_SHELL_DIR/build/scripts/params.tcl
source $HDK_SHELL_DIR/build/scripts/uram_options.tcl

set synth_options "-no_lc -shreg_min_size 5 -fsm_extraction one_hot -resource_sharing auto $synth_uram_option"
set synth_directive "default"

#Set psip to 1 to enable Physical Synthesis in Placer
set psip 0

set link 1

set opt 1
set opt_options ""
set opt_directive "Explore"
set opt_preHookTcl "$HDK_SHELL_DIR/build/scripts/check_uram.tcl"
set opt_postHookTcl "$HDK_SHELL_DIR/build/scripts/apply_debug_constraints.tcl"

set place 1
set place_options ""
set place_directive "ExtraNetDelay_high"
set place_preHookTcl ""
set place_postHookTcl ""

set phys_opt 1
set phys_options ""
set phys_directive ""
set phys_directive "AggressiveExplore"
set phys_preHookTcl ""
set phys_postHookTcl ""

set route 1
set route_options "-tns_cleanup"
set route_directive "Explore"
set route_preHookTcl ""
set route_postHookTcl ""

set route_phys_opt 1
set post_phys_options ""
set post_phys_directive "AggressiveExplore"
set post_phys_preHookTcl ""
set post_phys_postHookTcl ""


Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@
source $HDK_SHELL_DIR/build/scripts/params.tcl
source $HDK_SHELL_DIR/build/scripts/uram_options.tcl

set synth_options "-no_lc -shreg_min_size 5 -fsm_extraction one_hot -resource_sharing auto $synth_uram_option"
set synth_options "-no_lc -shreg_min_size 5 -fsm_extraction one_hot -resource_sharing auto $synth_uram_option -retiming"
set synth_directive "default"

#Set psip to 1 to enable Physical Synthesis in Placer
Expand Down

0 comments on commit e2a9752

Please sign in to comment.