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Merge pull request #1789 from protech-engineering/protech
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Add Debug support for NEORV32
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@enjoy-digital
enjoy-digital authored Sep 26, 2023
2 parents 3d956af + a0f4c37 commit eda2221
Showing 1 changed file with 107 additions and 40 deletions.
147 changes: 107 additions & 40 deletions litex/soc/cores/cpu/neorv32/core.py
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Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,7 @@
# This file is part of LiteX.
#
# Copyright (c) 2022 Florent Kermarrec <[email protected]>
# 2023 Protech Engineering <[email protected]>
# SPDX-License-Identifier: BSD-2-Clause

import os
Expand All @@ -17,7 +18,16 @@

# Variants -----------------------------------------------------------------------------------------

CPU_VARIANTS = ["minimal", "lite", "standard", "full"]
CPU_VARIANTS = [
"minimal",
"minimal+debug",
"lite",
"lite+debug",
"standard",
"standard+debug",
"full",
"full+debug",
]

# GCC Flags ----------------------------------------------------------------------------------------

Expand All @@ -30,9 +40,13 @@
# | ||||/-- Double-Precision Floating-Point
# i macfd
"minimal": "-march=rv32i2p0 -mabi=ilp32",
"minimal+debug": "-march=rv32i2p0 -mabi=ilp32",
"lite": "-march=rv32i2p0_mc -mabi=ilp32",
"lite+debug": "-march=rv32i2p0_mc -mabi=ilp32",
"standard": "-march=rv32i2p0_mc -mabi=ilp32",
"standard+debug": "-march=rv32i2p0_mc -mabi=ilp32",
"full": "-march=rv32i2p0_mc -mabi=ilp32",
"full+debug": "-march=rv32i2p0_mc -mabi=ilp32",
}

# NEORV32 ------------------------------------------------------------------------------------------
Expand All @@ -47,7 +61,7 @@ class NEORV32(CPU):
gcc_triple = CPU_GCC_TRIPLE_RISCV32
linker_output_format = "elf32-littleriscv"
nop = "nop"
io_regions = {0x8000_0000: 0x8000_0000} # Origin, Length.
io_regions = {0xF000_0000: 0x0FFF_BFFF} # Origin, Length.

# GCC Flags.
@property
Expand All @@ -67,8 +81,8 @@ def __init__(self, platform, variant="standard"):

# # #

# CPU LiteX Core Complex Wrapper
self.specials += Instance("neorv32_litex_core_complex",
# CPU Instance.
self.cpu_params = dict(
# Clk/Rst.
i_clk_i = ClockSignal("sys"),
i_rstn_i = ~(ResetSignal() | self.reset),
Expand All @@ -95,61 +109,110 @@ def __init__(self, platform, variant="standard"):
i_wb_err_i = idbus.err,
)

self.vhd2v_converter = VHD2VConverter(platform,
if "debug" in variant:
self.add_debug()

self.vhd2v_converter = VHD2VConverter(self.platform,
top_entity = "neorv32_litex_core_complex",
build_dir = os.path.abspath(os.path.dirname(__file__)),
work_package = "neorv32",
force_convert = True,
params = dict(
p_CONFIG = {
"minimal" : 0,
"lite" : 1,
"standard" : 2,
"full" : 3
}[variant],
p_DEBUG = False,
"minimal" : 0,
"minimal+debug" : 0,
"lite" : 1,
"lite+debug" : 1,
"standard" : 2,
"standard+debug" : 2,
"full" : 3,
"full+debug" : 3
}[self.variant],
p_DEBUG = "debug" in self.variant,
)
)

# Add Verilog sources
self.add_sources(variant)
self.add_sources()

# Memory Mapping.
@property
def mem_map(self):
return {
"rom" : 0x0000_0000,
"sram" : 0x0100_0000,
"main_ram" : 0x4000_0000,
"csr" : 0xF000_0000,
}

def set_reset_address(self, reset_address):
self.reset_address = reset_address
assert reset_address == 0x0000_0000

def add_sources(self, variant):
def add_debug(self):
self.i_jtag_trst = Signal()
self.i_jtag_tck = Signal()
self.i_jtag_tdi = Signal()
self.o_jtag_tdo = Signal()
self.i_jtag_tms = Signal()

self.cpu_params.update(
i_jtag_trst_i = self.i_jtag_trst,
i_jtag_tck_i = self.i_jtag_tck,
i_jtag_tdi_i = self.i_jtag_tdi,
o_jtag_tdo_o = self.o_jtag_tdo,
i_jtag_tms_i = self.i_jtag_tms,
)

def add_sources(self):
cdir = os.path.abspath(os.path.dirname(__file__))
# List VHDL sources.
sources = {
"core" : [
# CPU & Processors Packages/Cores.
"neorv32_package.vhd",
"neorv32_fifo.vhd",

# CPU components.
"neorv32_application_image.vhd",
"neorv32_bootloader_image.vhd",
"neorv32_boot_rom.vhd",
"neorv32_cfs.vhd",
"neorv32_cpu_alu.vhd",
"neorv32_cpu_control.vhd",
"neorv32_cpu_cp_bitmanip.vhd",
"neorv32_cpu_cp_cfu.vhd",
"neorv32_cpu_cp_fpu.vhd",
"neorv32_cpu_cp_muldiv.vhd",
"neorv32_cpu_cp_shifter.vhd",
"neorv32_cpu_decompressor.vhd",
"neorv32_cpu_lsu.vhd",
"neorv32_cpu_pmp.vhd",
"neorv32_cpu_regfile.vhd",
"neorv32_cpu.vhd",
"neorv32_cpu_alu.vhd",
"neorv32_cpu_cp_bitmanip.vhd",
"neorv32_cpu_cp_cfu.vhd",
"neorv32_cpu_cp_fpu.vhd",
"neorv32_cpu_cp_muldiv.vhd",
"neorv32_cpu_cp_shifter.vhd",
"neorv32_cpu_bus.vhd",
"neorv32_cpu_control.vhd",
"neorv32_cpu_decompressor.vhd",
"neorv32_cpu_regfile.vhd",

# Processor components.
"neorv32_crc.vhd",
"neorv32_dcache.vhd",
"neorv32_debug_dm.vhd",
"neorv32_debug_dtm.vhd",
"neorv32_dma.vhd",
"neorv32_dmem.entity.vhd",
"neorv32_fifo.vhd",
"neorv32_gpio.vhd",
"neorv32_gptmr.vhd",
"neorv32_icache.vhd",
"neorv32_imem.entity.vhd",
"neorv32_intercon.vhd",
"neorv32_mtime.vhd",
"neorv32_neoled.vhd",
"neorv32_onewire.vhd",
"neorv32_package.vhd",
"neorv32_pwm.vhd",
"neorv32_sdi.vhd",
"neorv32_slink.vhd",
"neorv32_spi.vhd",
"neorv32_sysinfo.vhd",
"neorv32_top.vhd",
"neorv32_icache.vhd",
"neorv32_busswitch.vhd",
"neorv32_bus_keeper.vhd",
"neorv32_wishbone.vhd",
"neorv32_mtime.vhd",
"neorv32_sysinfo.vhd",
"neorv32_debug_dm.vhd",
"neorv32_debug_dtm.vhd",
"neorv32_trng.vhd",
"neorv32_twi.vhd",
"neorv32_uart.vhd",
"neorv32_wdt.vhd",
"neorv32_wishbone.vhd",
"neorv32_xip.vhd",
"neorv32_xirq.vhd",
],

"core/mem": [
Expand All @@ -163,7 +226,8 @@ def add_sources(self, variant):
}

# Download VHDL sources (if not already present).
sha1 = "d610a0bd777f55d17dd59f174566aa88e911a1ec"
# Version 1.8.9
sha1 = "fdb00a5d24e256ac9a9cb29410f2653c95068c91"
for directory, vhds in sources.items():
for vhd in vhds:
self.vhd2v_converter.add_source(os.path.join(cdir, vhd))
Expand All @@ -172,3 +236,6 @@ def add_sources(self, variant):

def do_finalize(self):
assert hasattr(self, "reset_address")

# CPU LiteX Core Complex Wrapper
self.specials += Instance("neorv32_litex_core_complex", **self.cpu_params)

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