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Merge pull request #2139 from piotro888/pll-intel-reset
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cores/clock/intel: add reset to Intel PLLs
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enjoy-digital authored Dec 18, 2024
2 parents 1b47407 + e18e274 commit a6bdbed
Showing 1 changed file with 8 additions and 1 deletion.
9 changes: 8 additions & 1 deletion litex/soc/cores/clock/intel_common.py
Original file line number Diff line number Diff line change
Expand Up @@ -105,8 +105,15 @@ def compute_config(self):
return best_config
raise ValueError("No PLL config found")

def add_reset_delay(self, cycles):
for _ in range(cycles):
reset = Signal()
self.specials += Instance("DFFE", i_clk=self.clkin, i_d=self.reset, o_q=reset, i_ena=1, i_clrn=1, i_prn=1)
self.reset = reset

def do_finalize(self):
assert hasattr(self, "clkin")
self.add_reset_delay(cycles=8) # Prevents interlock when reset driven from sys_clk.
config = self.compute_config()
clks = Signal(self.nclkouts)
self.params.update(
Expand All @@ -116,7 +123,7 @@ def do_finalize(self):
p_OPERATION_MODE = "NORMAL",
i_INCLK = self.clkin,
o_CLK = clks,
i_ARESET = 0,
i_ARESET = self.reset,
i_CLKENA = 2**self.nclkouts_max - 1,
i_EXTCLKENA = 0xf,
i_FBIN = 1,
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