backwards compatibility with python3.7

enjoy-digital · Dec 21, 2024 · 9f5c3d0 · 9f5c3d0
1 parent 57333ee
commit 9f5c3d0
Showing 1 changed file with 2 additions and 1 deletion.
diff --git a/litex/soc/cores/clock/xilinx_usp.py b/litex/soc/cores/clock/xilinx_usp.py
@@ -143,7 +143,8 @@ def compute_config(self) -> Dict[str, Any]:
 
                     dividers = list(clkdiv_range(*self.clkout_divide_range))
                     # Add specific range dividers if they exist
-                    if specific_div_range := getattr(self, f"clkout{n}_divide_range", None):
+                    specific_div_range = getattr(self, f"clkout{n}_divide_range", None)
+                    if specific_div_range:
                         dividers.extend(clkdiv_range(*specific_div_range))
 
                     # For clkout0, CLKOUT[0]_DIVIDE_F also has range 2.0 to 128.0 with step 0.125