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Wb address fix #48

Merged
merged 7 commits into from
Oct 2, 2022
Merged

Wb address fix #48

merged 7 commits into from
Oct 2, 2022

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jeffdi
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@jeffdi jeffdi commented Sep 28, 2022

Changes to correct wb address issues for the user project and housekeeping. Also correct duplicate assign statements in the verilog as well as adds power pins for SRAM and VexRiscv.

Several testbenches also added.

Fixes issue #10 , #45 , #38 , #46

- hk still limited to 0x8000000 due to issue with SoCRegion mask generation
- added script to fix debug logic after rtl generation of mgmt core
- hk still limited to 0x8000000 due to issue with SoCRegion mask generation
- added script to fix debug logic after rtl generation of mgmt core
- added testbenches for sys control and hkspi
- reconciled def.h with caravel.h
- added testbenches for sys control and hkspi
- reconciled def.h with caravel.h
@shalan shalan merged commit 5fc7d78 into caravel_redesign Oct 2, 2022
@RTimothyEdwards RTimothyEdwards added flow Changes to Makefile and process flow RTL Changes to verilog source simulation Verilog testbenches and simulation error Something isn't working labels Oct 4, 2022
@jeffdi jeffdi linked an issue Oct 8, 2022 that may be closed by this pull request
@jeffdi jeffdi removed a link to an issue Oct 8, 2022
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error Something isn't working flow Changes to Makefile and process flow RTL Changes to verilog source simulation Verilog testbenches and simulation
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