Merge pull request #19 from efabless/includes_fix

Include files from user_project
efabless · Feb 25, 2022 · 9e29d83 · 9e29d83
2 parents 76d6c61 + ec53a41
commit 9e29d83
Show file tree

Hide file tree

Showing 5 changed files with 34 additions and 86 deletions.
diff --git a/verilog/dv/make/sim.makefile b/verilog/dv/make/sim.makefile
@@ -63,22 +63,45 @@ hex:  ${BLOCKS:=.hex}
 
 ## RTL
 ifeq ($(SIM),RTL)
-	iverilog -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
-	-f$(VERILOG_PATH)/includes/includes.rtl.$(CONFIG) -o $@ $<
+    ifeq ($(CONFIG),caravel_user_project)
+		iverilog -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+        -f$(VERILOG_PATH)/includes/includes.rtl.caravel \
+        -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o $@ $<
+    else
+		iverilog -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+		-f$(VERILOG_PATH)/includes/includes.rtl.$(CONFIG) \
+		-f$(CARAVEL_PATH)/rtl/__user_project_wrapper.v -o $@ $<
+    endif
 endif 
 
 ## GL
 ifeq ($(SIM),GL)
-	iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
-        -f$(VERILOG_PATH)/includes/includes.gl.$(CONFIG) -o $@ $<
+    ifeq ($(CONFIG),caravel_user_project)
+		iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+        -f$(VERILOG_PATH)/includes/includes.gl.caravel \
+        -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o $@ $<
+    else
+		iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
+        -f$(VERILOG_PATH)/includes/includes.gl.$(CONFIG) \
+		-f$(CARAVEL_PATH)/gl/__user_project_wrapper.v -o $@ $<
+    endif
 endif 
 
 ## GL+SDF
 ifeq ($(SIM),GL_SDF)
-	cvc64  +interp \
-	+define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY +define+ENABLE_SDF \
-	+change_port_type +dump2fst +fst+parallel2=on   +nointeractive +notimingchecks +mipdopt \
-	 -f $(VERILOG_PATH)/includes/includes.gl+sdf.$(CONFIG) $<
+    ifeq ($(CONFIG),caravel_user_project)
+		cvc64  +interp \
+		+define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY +define+ENABLE_SDF \
+		+change_port_type +dump2fst +fst+parallel2=on   +nointeractive +notimingchecks +mipdopt \
+		-f $(VERILOG_PATH)/includes/includes.gl+sdf.caravel \
+		-f $(USER_PROJECT_VERILOG)/includes/includes.gl+sdf.$(CONFIG) $<
+	else
+		cvc64  +interp \
+		+define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY +define+ENABLE_SDF \
+		+change_port_type +dump2fst +fst+parallel2=on   +nointeractive +notimingchecks +mipdopt \
+		-f $(VERILOG_PATH)/includes/includes.gl+sdf.$(CONFIG) \
+		-f $CARAVEL_PATH/gl/__user_project_wrapper.v $<
+    endif
 endif
 
 %.vcd: %.vvp

diff --git a/verilog/includes/includes.gl+sdf.caravel b/verilog/includes/includes.gl+sdf.caravel
@@ -38,7 +38,7 @@ $CARAVEL_PATH/gl/spare_logic_block.v
 $CARAVEL_PATH/gl/housekeeping.v 		
 $CARAVEL_PATH/gl/caravel_clocking.v		
 $CARAVEL_PATH/gl/digital_pll.v  		
-$CARAVEL_PATH/gl/__user_project_wrapper.v	
+// $CARAVEL_PATH/gl/__user_project_wrapper.v	
 $CARAVEL_PATH/gl/user_id_programming.v  	
 $CARAVEL_PATH/gl/caravel.v			
 

diff --git a/verilog/includes/includes.gl.caravel b/verilog/includes/includes.gl.caravel
@@ -56,7 +56,7 @@
 -v $(CARAVEL_PATH)/gl/housekeeping.v		     
 -v $(CARAVEL_PATH)/gl/caravel_clocking.v	     
 -v $(CARAVEL_PATH)/gl/digital_pll.v		     
--v $(CARAVEL_PATH)/gl/__user_project_wrapper.v	     
+#-v $(CARAVEL_PATH)/gl/__user_project_wrapper.v	     
 -v $(CARAVEL_PATH)/gl/user_id_programming.v	     
 -v $(CARAVEL_PATH)/gl/caravel.v 		     
 

diff --git a/verilog/includes/includes.rtl.caravel b/verilog/includes/includes.rtl.caravel
@@ -44,7 +44,7 @@
 -v $(CARAVEL_PATH)/rtl/housekeeping.v		     
 -v $(CARAVEL_PATH)/rtl/caravel_clocking.v	     
 -v $(CARAVEL_PATH)/rtl/digital_pll.v		     
--v $(CARAVEL_PATH)/rtl/__user_project_wrapper.v	     
+#-v $(CARAVEL_PATH)/rtl/__user_project_wrapper.v	     
 -v $(CARAVEL_PATH)/rtl/user_id_programming.v	     
 -v $(CARAVEL_PATH)/rtl/caravel.v 		     
 

diff --git a/verilog/includes/includes.rtl.caravel_user_project b/verilog/includes/includes.rtl.caravel_user_project