Finished design for a superscalar pipeline processor in functional Verilog. Runs a cache based memory system, a branch predictor, and a 2-way superscalar pipeline processor issuing two instructions at a time. The project was to be completed over a course of an academic quarter and the design is intended for Yiming Gan and Dylan Vanmali, the creators of the project.
Check out the report located under the file final_report.pdf for a visual of this design and report of our findings!