[Backport] 8276799: Implementation of JEP 422: Linux/RISC-V Port #800
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Summary: sync with riscv upstream riscv-port-jdk11u This is a combination of multiple patches. Revert "[Misc] Add failed test cases to linux-riscv problem list" Revert "[Misc] RISC-V backend build broken after merging VectorAPI" Revert "[Backport] 8297476: Increase InlineSmallCode default from 1000 to 2500 for RISC-V" Revert "[RISCV] Backport ShenandoahGC specific code" Revert "[Backport] 8296771: RISC-V: C2: assert(false) failed: bad AD file" Revert "[Misc] Fix ported TestLibmIntrinsics.java" Revert "[Backport] 8295926: RISC-V: C1: Fix LIRGenerator::do_LibmIntrinsic" Revert "[Backport] 8293100: RISC-V: Need to save and restore callee-saved FloatRegisters in StubGenerator::generate_call_stub" Revert "[Backport] 8278743: riscv: Remove the x4 register saving logic in Java frames" Revert "[Backport] 8287418: riscv: Fix correctness issue of MacroAssembler::movptr" Revert "[RISCV] Backport RVV and support RVV-0.7.1" Revert "[RISCV] support paired memory instruction in CSky (dragonwell-project#217)" Revert "[Backport] Backport RISC-V backend code from the openjdk/riscv-port repo's initial load" 8276799: Implementation of JEP 422: Linux/RISC-V Port 8283737: riscv: MacroAssembler::stop() should emit fixed-length instruction sequence 8285437: riscv: Fix MachNode size mismatch for MacroAssembler::verify_oops* 8287418: riscv: Fix correctness issue of MacroAssembler::movptr 8293100: RISC-V: Need to save and restore callee-saved FloatRegisters in StubGenerator::generate_call_stub 8295926: RISC-V: C1: Fix LIRGenerator::do_LibmIntrinsic 8291952: riscv: Remove PRAGMA_NONNULL_IGNORED 8308277: RISC-V: Improve vectorization of Match.sqrt() on floats 8282306: os::is_first_C_frame(frame*) crashes on invalid link access [RISCV] support paired memory instruction in CSky (dragonwell-project#217) [RISCV] Backport RVV and support RVV-0.7.1 [Misc] Fix build/test failre after riscv port Testing: jtreg tier1~3 Reviewers: sendaoYan, yulei Issue: https://aone.alibaba-inc.com/v2/project/355606/req/55189627 CR: dragonwell-project#800
Summary: sync with riscv upstream riscv-port-jdk11u This is a combination of multiple patches. Revert "[Misc] Add failed test cases to linux-riscv problem list" Revert "[Misc] RISC-V backend build broken after merging VectorAPI" Revert "[Backport] 8297476: Increase InlineSmallCode default from 1000 to 2500 for RISC-V" Revert "[RISCV] Backport ShenandoahGC specific code" Revert "[Backport] 8296771: RISC-V: C2: assert(false) failed: bad AD file" Revert "[Misc] Fix ported TestLibmIntrinsics.java" Revert "[Backport] 8295926: RISC-V: C1: Fix LIRGenerator::do_LibmIntrinsic" Revert "[Backport] 8293100: RISC-V: Need to save and restore callee-saved FloatRegisters in StubGenerator::generate_call_stub" Revert "[Backport] 8278743: riscv: Remove the x4 register saving logic in Java frames" Revert "[Backport] 8287418: riscv: Fix correctness issue of MacroAssembler::movptr" Revert "[RISCV] Backport RVV and support RVV-0.7.1" Revert "[RISCV] support paired memory instruction in CSky (dragonwell-project#217)" Revert "[Backport] Backport RISC-V backend code from the openjdk/riscv-port repo's initial load" 8276799: Implementation of JEP 422: Linux/RISC-V Port 8283737: riscv: MacroAssembler::stop() should emit fixed-length instruction sequence 8285437: riscv: Fix MachNode size mismatch for MacroAssembler::verify_oops* 8287418: riscv: Fix correctness issue of MacroAssembler::movptr 8293100: RISC-V: Need to save and restore callee-saved FloatRegisters in StubGenerator::generate_call_stub 8295926: RISC-V: C1: Fix LIRGenerator::do_LibmIntrinsic 8291952: riscv: Remove PRAGMA_NONNULL_IGNORED 8308277: RISC-V: Improve vectorization of Match.sqrt() on floats 8282306: os::is_first_C_frame(frame*) crashes on invalid link access [RISCV] support paired memory instruction in CSky (dragonwell-project#217) [RISCV] Backport RVV and support RVV-0.7.1 [Misc] Fix build/test failre after riscv port Testing: jtreg tier1~3 Reviewers: sendaoYan, yulei Issue: dragonwell-project#801 CR: dragonwell-project#800
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Summary: sync with riscv upstream riscv-port-jdk11u
This is a combination of multiple patches.
Revert "[Misc] Add failed test cases to linux-riscv problem list"
Revert "[Misc] RISC-V backend build broken after merging VectorAPI"
Revert "[Backport] 8297476: Increase InlineSmallCode default from 1000 to 2500 for RISC-V"
Revert "[RISCV] Backport ShenandoahGC specific code"
Revert "[Backport] 8296771: RISC-V: C2: assert(false) failed: bad AD file"
Revert "[Misc] Fix ported TestLibmIntrinsics.java"
Revert "[Backport] 8295926: RISC-V: C1: Fix LIRGenerator::do_LibmIntrinsic"
Revert "[Backport] 8293100: RISC-V: Need to save and restore callee-saved FloatRegisters in StubGenerator::generate_call_stub"
Revert "[Backport] 8278743: riscv: Remove the x4 register saving logic in Java frames"
Revert "[Backport] 8287418: riscv: Fix correctness issue of MacroAssembler::movptr"
Revert "[RISCV] Backport RVV and support RVV-0.7.1"
Revert "[RISCV] support paired memory instruction in CSky (#217)"
Revert "[Backport] Backport RISC-V backend code from the openjdk/riscv-port repo's initial load"
8276799: Implementation of JEP 422: Linux/RISC-V Port
8283737: riscv: MacroAssembler::stop() should emit fixed-length instruction sequence
8285437: riscv: Fix MachNode size mismatch for MacroAssembler::verify_oops*
8287418: riscv: Fix correctness issue of MacroAssembler::movptr
8293100: RISC-V: Need to save and restore callee-saved FloatRegisters in StubGenerator::generate_call_stub
8295926: RISC-V: C1: Fix LIRGenerator::do_LibmIntrinsic
8291952: riscv: Remove PRAGMA_NONNULL_IGNORED
8308277: RISC-V: Improve vectorization of Match.sqrt() on floats
8282306: os::is_first_C_frame(frame*) crashes on invalid link access
[RISCV] support paired memory instruction in CSky (#217)
[RISCV] Backport RVV and support RVV-0.7.1
[Misc] Fix build/test failre after riscv port
Testing: jtreg tier1~3
Reviewers: sendaoYan, yulei
Issue: #801
CR: #800