[RISCV] Port RISCV patch for JDK11u to Dragonwell11 #799
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This reverts commit 04af404.
This reverts commit 8df29ae.
…0 to 2500 for RISC-V" This reverts commit 7f93d83.
This reverts commit 1985612.
…file" This reverts commit 416bd09.
This reverts commit d0f426b.
…insic" This reverts commit f875de7.
…aved FloatRegisters in StubGenerator::generate_call_stub" This reverts commit 9d960b6.
…c in Java frames" This reverts commit 54fca39.
…mbler::movptr" This reverts commit 81d9f79.
This reverts commit 3af0c4a.
…-project#217)" This reverts commit 4b1a5c2.
…v-port repo's initial load" This reverts commit 959fa35.
8283737: riscv: MacroAssembler::stop() should emit fixed-length instruction sequence 8285437: riscv: Fix MachNode size mismatch for MacroAssembler::verify_oops* 8287418: riscv: Fix correctness issue of MacroAssembler::movptr 8293100: RISC-V: Need to save and restore callee-saved FloatRegisters in StubGenerator::generate_call_stub 8295926: RISC-V: C1: Fix LIRGenerator::do_LibmIntrinsic 8291952: riscv: Remove PRAGMA_NONNULL_IGNORED 8308277: RISC-V: Improve vectorization of Match.sqrt() on floats 8282306: os::is_first_C_frame(frame*) crashes on invalid link access Co-authored-by: Xiaolin Zheng <[email protected]> Reviewed-by: fyang Backport-of: 5905b02c0e2643ae8d097562f181953f6c88fc89
…#217) Summary: add UseCSky option to enable csky instructions merge ld/st into paired memory instructions Test Plan: SPECjbb2005 Reviewed-by: yunyao Issue: dragonwell-project#216 CR: dragonwell-project#217
Summary: Backport and support RVV 0.7.1 on boards Test Plan: jtregs Reviewed-by: kuaiwei Issue: dragonwell-project#209 CR: dragonwell-project#295
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[Backport] Port RISCV patch for JDK11u to Dragonwell11
Summary: sync with riscv upstream riscv-port-jdk11u
Test Plan: jtreg tier1~3
Reviewed-by:
Issue: https://aone.alibaba-inc.com/v2/project/355606/req/55189627
CR: #799