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FIX: Working documentation
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daquintero committed Jun 21, 2023
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109 changes: 109 additions & 0 deletions docs/autoapi/piel/cocotb/index.rst
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:py:mod:`piel.cocotb`
=====================

.. py:module:: piel.cocotb
.. autoapi-nested-parse::

The objective of this file is to provide the simulation ports and interconnection to consider modelling digital and mixed signal logic.

The main simulation driver is cocotb, and this generates a set of files that correspond to time-domain digital simulations.
The cocotb verification software can also be used to perform mixed signal simulation, and digital data can be inputted as a bitstream into a photonic solver, although the ideal situation would be to have integrated photonic time-domain models alongside the electronic simulation solver, and maybe this is where it will go. It can be assumed that, as is currently, cocotb can interface python with multiple solvers until someone (and I'd love to do this) writes an equivalent python-based or C++ based python time-domain simulation solver.

The nice thing about cocotb is that as long as the photonic simulations can be written asyncrhonously, time-domain simulations can be closely integrated or simulated through this verification software.



Module Contents
---------------


Functions
~~~~~~~~~

.. autoapisummary::

piel.cocotb.check_cocotb_testbench_exists
piel.cocotb.configure_cocotb_simulation
piel.cocotb.run_cocotb_simulation



Attributes
~~~~~~~~~~

.. autoapisummary::

piel.cocotb.write_cocotb_makefile
piel.cocotb.make_cocotb


.. py:function:: check_cocotb_testbench_exists(design_directory: str | pathlib.Path) -> bool
Checks if a cocotb testbench exists in the design directory.

:param design_directory: Design directory.
:type design_directory: str | pathlib.Path

:returns: True if cocotb testbench exists.
:rtype: cocotb_testbench_exists(bool)


.. py:function:: configure_cocotb_simulation(design_directory: str | pathlib.Path, simulator: Literal[icarus, verilator], top_level_language: Literal[verilog, vhdl], top_level_verilog_module: str, test_python_module: str, design_sources_list: list | None = None)
Writes a cocotb makefile.

If no design_sources_list is provided then it adds all the design sources under the `src` folder.

In the form::
Makefile
# defaults
SIM ?= icarus
TOPLEVEL_LANG ?= verilog

VERILOG_SOURCES += $(PWD)/my_design.sv
# use VHDL_SOURCES for VHDL files

# TOPLEVEL is the name of the toplevel module in your Verilog or VHDL file
TOPLEVEL = my_design

# MODULE is the basename of the Python test file
MODULE = test_my_design

# include cocotb's make rules to take care of the simulator setup
include $(shell cocotb-config --makefiles)/Makefile.sim


:param design_directory: The directory where the design is located.
:type design_directory: str | pathlib.Path
:param simulator: The simulator to use.
:type simulator: Literal["icarus", "verilator"]
:param top_level_language: The top level language.
:type top_level_language: Literal["verilog", "vhdl"]
:param top_level_verilog_module: The top level verilog module.
:type top_level_verilog_module: str
:param test_python_module: The test python module.
:type test_python_module: str
:param design_sources_list: A list of design sources. Defaults to None.
:type design_sources_list: list | None, optional

:returns: None


.. py:function:: run_cocotb_simulation(design_directory: str) -> subprocess.CompletedProcess
Equivalent to running the cocotb makefile::
make

:param design_directory: The directory where the design is located.
:type design_directory: str

:returns: The subprocess.CompletedProcess object.
:rtype: subprocess.CompletedProcess


.. py:data:: write_cocotb_makefile
.. py:data:: make_cocotb
80 changes: 75 additions & 5 deletions docs/autoapi/piel/file_system/index.rst
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Expand Up @@ -13,22 +13,92 @@ Functions

.. autoapisummary::

piel.file_system.check_example_design
piel.file_system.copy_source_folder
piel.file_system.permit_script_execution
piel.file_system.return_path
piel.file_system.run_script
piel.file_system.setup_example_design
piel.file_system.check_example_design
piel.file_system.write_script



.. py:function:: copy_source_folder(source_directory: str, target_directory: str)
.. py:function:: check_example_design(design_name: str | pathlib.Path = 'simple_design') -> bool
We copy the example simple_design from docs to the `/foss/designs` in the `iic-osic-tools` environment.

.. py:function:: setup_example_design(project_source: Literal[piel, openlane] = 'piel', example_name: str = 'simple_design')
:param design_name: Name of the design to check.
:type design_name: str

:returns: None


.. py:function:: copy_source_folder(source_directory: str | pathlib.Path, target_directory: str | pathlib.Path) -> None
Copies the files from a source_directory to a target_directory

:param source_directory: Source directory.
:type source_directory: str
:param target_directory: Target directory.
:type target_directory: str

:returns: None


.. py:function:: permit_script_execution(script_path: str | pathlib.Path) -> None
Permits the execution of a script.

:param script_path: Script path.
:type script_path: str

:returns: None

We copy the example simple_design from docs to the `/foss/designs` in the `iic-osic-tools` environment.

.. py:function:: return_path(input_path: str | pathlib.Path) -> pathlib.Path
.. py:function:: check_example_design(example_name: str = 'simple_design')
Returns a pathlib.Path to be able to perform operations accordingly internally.

This allows us to maintain compatibility between POSIX and Windows systems.

:param input_path: Input path.
:type input_path: str

:returns: Pathlib path.
:rtype: pathlib.Path


.. py:function:: run_script(script_path: str | pathlib.Path) -> None
Runs a script on the filesystem `script_path`.

:param script_path: Script path.
:type script_path: str

:returns: None


.. py:function:: setup_example_design(project_source: Literal[piel, openlane] = 'piel', example_name: str = 'simple_design') -> None
We copy the example simple_design from docs to the `/foss/designs` in the `iic-osic-tools` environment.

:param project_source: Source of the project.
:type project_source: str
:param example_name: Name of the example design.
:type example_name: str

:returns: None


.. py:function:: write_script(directory_path: str | pathlib.Path, script: str, script_name: str) -> None
Records a `script_name` in the `scripts` project directory.

:param directory_path: Design directory.
:type directory_path: str
:param script: Script to write.
:type script: str
:param script_name: Name of the script.
:type script_name: str

:returns: None
14 changes: 11 additions & 3 deletions docs/autoapi/piel/gdsfactory/index.rst
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.. autoapisummary::

piel.gdsfactory.create_gdsfactory_component
piel.gdsfactory.create_gdsfactory_component_from_openlane



.. py:function:: create_gdsfactory_component(design_directory: str) -> gdsfactory.Component
.. py:function:: create_gdsfactory_component_from_openlane(design_directory: str | pathlib.Path, run_name: str | None = None) -> gdsfactory.Component
This function cretes a gdsfactory component that can be included in the network codesign of the device, or that can be used for interconnection codesign.
This function cretes a gdsfactory layout component that can be included in the network codesign of the device, or that can be used for interconnection codesign.

It will look into the latest design run and extract the final OpenLane-generated GDS. You do not have to have run this with OpenLane2 as it just looks at the latest run.

:param design_directory: Design directory PATH.
:type design_directory: str
:param run_name: Name of the run to extract the GDS from. If None, it will look at the latest run.
:type run_name: str

:returns: GDSFactory component.
:rtype: component(gf.Component)
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