continue finishing the examples

docs/examples/03a_sax_cocotb_cosimulation.py

@@ -339,7 +339,8 @@
         "output_amplitude_array_0_abs",
         "output_amplitude_array_0_phase_deg",
     ],
-    y_axis_title_list=["e1 Phase", "o3 Amplitude", "o3 Phase"],
+    y_label=[r"$|e1|$ (abs)", r"$|o3|$ (abs)", r"$deg(o3)$"],
+    x_label="time (ns)",
 )
 simple_ideal_o3_mzi_2x2_plots.savefig(
     "../_static/img/examples/03a_sax_active_cosimulation/simple_ideal_o3_mzi_2x2_plots.PNG"
@@ -355,7 +356,7 @@
         "output_amplitude_array_1_abs",
         "output_amplitude_array_1_phase_deg",
     ],
-    y_axis_title_list=["e1 Phase", "o4 Amplitude", "o4 Phase"],
+    y_label=[r"|e1| (abs)", r"$|o4|$ (abs)", r"$deg(o4)$"],
 )
 simple_ideal_o4_mzi_2x2_plots.savefig(
     "../_static/img/examples/03a_sax_active_cosimulation/simple_ideal_o4_mzi_2x2_plots.PNG"
@@ -787,7 +788,7 @@ def switch_lattice_phase_array_to_state(
             "out_o_" + str(port_i) + "_abs",
             "out_o_" + str(port_i) + "_phase_deg",
         ],
-        y_axis_title_list=[
+        y_label=[
             "e1,5 Phase",
             "o" + str(port_i) + "Amplitude",
             "o" + str(port_i) + "Phase",

docs/examples/04_spice_cosimulation/04_spice_cosimulation.py

@@ -105,6 +105,9 @@
 
 # So this is very cool, we have our device model giving us electrical data when connected to the geometrical design parameters. What effect does half that resistance have on the driver though? We need to first create a SPICE model of our circuit. One of the main complexities now is that we need to create a mapping between our component models and `hdl21` which is dependent on our device model extraction. Another functionality we might desire is to validate physical electrical connectivity by simulating the circuit accordingly.
 
+from gdsfactory.export import to_svg
+to_svg(our_short_resistive_mzi_2x2_2x2_phase_shifter)
+
 # ## Extracting the SPICE circuit and assigning model parameters
 
 # We will exemplify how `piel` microservices enable the extraction and configuration of the SPICE circuit. This is done by implementing a SPICE netlist construction backend to the circuit composition functions in `sax`, and is composed in a way that is then integrated into `hdl21` or any SPICE-based solver through the `VLSIR` `Netlist`.
@@ -320,6 +323,12 @@
 
 # So this seems equivalent to the gdsfactory component representation. We can now continue to implement our SPICE simulation.
 
+# ### Flow Automation
+
+piel.flows.extract_component_spice_from_netlist(
+    component=straight_heater_metal_simple(),
+)
+
 # ## `SPICE` Integration
 
 # We have seen in the previous example how to integrate digital-driven data with photonic circuit steady-state simulations. However, this is making a big assumption: whenever digital codes are applied to photonic components, the photonic component responds immediately. We need to account for the electrical load physics in order to perform more accurate simulation models of our systems.
@@ -388,7 +397,7 @@ class OperatingPointTb:
 
 # We can now run the simulation using `ngpsice`. Make sure you have it installed, although this will be automatic in the *IIC-OSIC-TOOLS* environment:
 
-results = piel.run_simulation(simulation=simple_operating_point_simulation)
+results = piel.run_simulation(sistraight_heater_metal_simple()mulation=simple_operating_point_simulation)
 results
 
 # ```python
@@ -478,15 +487,12 @@ class TransientTb:
 
 # We can plot our simulation data accordingly:
 
-simple_transient_plot = piel.visual.plot_simple_multi_row(
-    data=transient_simulation_results,
-    x_axis_column_name="time",
-    row_list=[
-        "v(xtop.vpulse_p)",
-        "i(v.xtop.vvpulse)",
-    ],
-    y_axis_title_list=["v(v.xtop.vvpulse)", "i(v.xtop.vvpulse)", "o4 Phase"],
-)
+simple_transient_plot = piel.visual.plot_simple_multi_row(data=transient_simulation_results, x_axis_column_name="time",
+                                                          row_list=[
+                                                              "v(xtop.vpulse_p)",
+                                                              "i(v.xtop.vvpulse)",
+                                                          ], y_label=["v(v.xtop.vvpulse)", "i(v.xtop.vvpulse)",
+                                                                      "o4 Phase"])
 simple_transient_plot.savefig(
     "../../_static/img/examples/04_spice_cosimulation/simple_transient_plot.PNG"
 )
@@ -537,15 +543,11 @@ class TransientTb:
 # | 39 |        39 | 0.00295 |           -0.61  |          0.00061  |        -0.0003721   |                   1000 |
 #
 
-simple_transient_plot_power_resistance = piel.visual.plot_simple_multi_row(
-    data=transient_simulation_results,
-    x_axis_column_name="time",
-    row_list=[
+simple_transient_plot_power_resistance = piel.visual.plot_simple_multi_row(data=transient_simulation_results,
+                                                                           x_axis_column_name="time", row_list=[
         "resistance(xtop.vpulse)",
         "power(xtop.vpulse)",
-    ],
-    y_axis_title_list=[r"resistance ($\Omega$)", r"power ($W$)"],
-)
+    ], y_label=[r"resistance ($\Omega$)", r"power ($W$)"])
 simple_transient_plot_power_resistance.savefig(
     "../../_static/img/examples/04_spice_cosimulation/simple_transient_plot_power_resistance.PNG"
 )
@@ -571,18 +573,14 @@ class TransientTb:
 
 # A full visualisation of the signal is including the cumulative energy use:
 
-simple_transient_plot_full = piel.visual.plot_simple_multi_row(
-    data=transient_simulation_results,
-    x_axis_column_name="time",
-    row_list=[
+simple_transient_plot_full = piel.visual.plot_simple_multi_row(data=transient_simulation_results,
+                                                               x_axis_column_name="time", row_list=[
         "v(xtop.vpulse_p)",
         "i(v.xtop.vvpulse)",
         "resistance(xtop.vpulse)",
         "power(xtop.vpulse)",
         "energy_consumed(xtop.vpulse)",
-    ],
-    y_axis_title_list=[r"$V$", r"$A$", r"$\Omega$", r"$W$", r"$J$"],
-)
+    ], y_label=[r"$V$", r"$A$", r"$\Omega$", r"$W$", r"$J$"])
 simple_transient_plot_full.savefig(
     "../../_static/img/examples/04_spice_cosimulation/simple_transient_plot_full.PNG"
 )
@@ -703,30 +701,26 @@ def linear_phase_mapping(power_w: float) -> float:
 
 simple_ideal_o3_mzi_2x2_plots = piel.visual.plot_simple_multi_row(
     data=transient_simulation_results,
-    x_axis_column_name="time",
-    row_list=[
+    x_axis_column_name="time", row_list=[
         "power(xtop.vpulse)",
         "output_amplitude_array_0_abs",
         "output_amplitude_array_0_phase_deg",
     ],
-    y_axis_title_list=["e1 Power", "o3 Amplitude", "o3 Phase"],
+    y_label=[r"$|e1|$ (W)", r"$|o3|$ (abs)", r"$deg(o3)$"],
+    x_label="time (s)"
 )
 simple_ideal_o3_mzi_2x2_plots.savefig(
     "../../_static/img/examples/04_spice_cosimulation/simple_ideal_o3_mzi_2x2_plots.PNG"
 )
 
 # ![simple_ideal_o3_mzi_2x2_plots](../../_static/img/examples/04_spice_cosimulation/simple_ideal_o3_mzi_2x2_plots.PNG)
 
-simple_ideal_o4_mzi_2x2_plots = piel.visual.plot_simple_multi_row(
-    data=transient_simulation_results,
-    x_axis_column_name="time",
-    row_list=[
+simple_ideal_o4_mzi_2x2_plots = piel.visual.plot_simple_multi_row(data=transient_simulation_results,
+                                                                  x_axis_column_name="time", row_list=[
         "power(xtop.vpulse)",
         "output_amplitude_array_1_abs",
         "output_amplitude_array_1_phase_deg",
-    ],
-    y_axis_title_list=["e1 Phase", "o4 Amplitude", "o4 Phase"],
-)
+    ], y_label=["e1 Phase", "o4 Amplitude", "o4 Phase"])
 simple_ideal_o4_mzi_2x2_plots.savefig(
     "../../_static/img/examples/04_spice_cosimulation/simple_ideal_o4_mzi_2x2_plots.PNG"
 )

docs/examples/07_full_flow_demo_electronic_photonic/07_full_flow_demo_electronic_photonic.py

@@ -104,6 +104,10 @@ def create_switch_fabric():
 chain_3_mode_lattice_circuit = create_switch_fabric()
 chain_3_mode_lattice_circuit
 
+from gdsfactory.export import to_svg
+
+to_svg(chain_3_mode_lattice_circuit)
+
 # ## 2. Extracting our optical-to-electronic control logic truth table
 
 
@@ -334,7 +338,7 @@ def create_switch_fabric():
         "output_amplitude_array_1_abs",
         "output_amplitude_array_1_phase_deg",
     ],
-    y_axis_title_list=["e1 Phase", "o4 Amplitude", "o4 Phase"],
+    y_label=["e1 Phase", "o4 Amplitude", "o4 Phase"],
 )
 simple_ideal_o4_mzi_2x2_plots.savefig(
     "../_static/img/examples/03a_sax_active_cosimulation/simple_ideal_o4_mzi_2x2_plots.PNG"

docs/sections/environment/index.rst

@@ -20,6 +20,15 @@ If you want to enter the corresponding `nix-shell` environment, you can run the
 
     $ piel environment activate
 
+It will print:
+
+.. code-block::
+
+    # Please run this in your shell:
+    nix shell github:efabless/nix-eda#{ngspice,xschem,verilator,yosys} github:efabless/openlane2 nixpkgs#verilog nixpkgs#gtkwave
+
+This is because, I believe, for security reasons it is very difficult to automatically enter a nix shell directly from python or a subprocess.
+
 `OpenLane 2 via nix <https://openlane2.readthedocs.io/en/latest/getting_started/index.html#nix-recommended>`__ have recently released another way to package their `python`-driven ``Openlane 2`` digital chip layout flow. We have previously had issues reproducibly building the `docker` configuration, and because most users are likely to use these tools for developing their chips rather than distributing software, `nix <https://nixos.org/>`__ might be well suited for these applications.
 
 .. include:: nix/development_installation.rst

docs/sections/environment/nix/development_installation.rst

@@ -15,13 +15,13 @@ Assuming you already have ``piel`` installed in a local environment, you can sim
     piel environment install-nix # To install nix
     piel environment install-openlane # To install openlane
 
-To enter the nix environment, run:
+To enter the nix environment that uses all the tools used within ``piel``, run:
 
 .. code:: bash
 
-    piel environment activate-piel-nix
-    # piel environment activate-openlane-nix # if you want to enter the openlane one instead
+    piel environment activate
 
+An important thing to note is that, for `openlane` to work properly, its `nix` configured binaries need to be untouched. This means we need to make sure that the virtualenviron
 
 System requirements
 ^^^^^^^^^^^^^^^^^^^^^^

piel/flows/__init__.py

@@ -1,8 +1,9 @@
+from .analog_photonic import extract_component_spice_from_netlist
 from .digital_logic import (
     generate_verilog_and_verification_from_truth_table,
     read_simulation_data_to_truth_table,
     run_verification_simulation_for_design,
-    layout_truth_table
+    layout_truth_table,
 )
 from .digital_electro_optic import (
     add_truth_table_phase_to_bit_data,

piel/flows/analog_photonic.py

@@ -0,0 +1,45 @@
+"""
+This file contains the design flow from going from a photonic component into an analogue.
+"""
+import sys
+import hdl21 as h
+from piel.types import CircuitComponent, PathTypes
+from piel.integration import (
+    gdsfactory_netlist_with_hdl21_generators,
+    construct_hdl21_module,
+)
+
+
+def extract_component_spice_from_netlist(
+    component: CircuitComponent, output_path: PathTypes = sys.stdout, fmt: str = "spice"
+):
+    """
+    This function extracts the SPICE netlist from a component definition and writes it to a file. The function uses
+    the HDL21 library to generate the SPICE netlist from the component's netlist. The netlist is then written to a
+    file in the specified format.
+
+    Args:
+        component (CircuitComponent): The component for which to extract the SPICE netlist.
+        output_path (str): The path to the output file where the SPICE netlist will be written.
+        fmt (str, optional): The format in which the netlist will be written. Defaults to "spice".
+
+    Returns:
+        None
+    """
+    # Get the netlist of the component
+    component_netlist = component.get_netlist(
+        allow_multiple=True, exclude_port_types="optical"
+    )
+
+    #
+    spice_component_netlist = gdsfactory_netlist_with_hdl21_generators(
+        component_netlist
+    )
+
+    hdl21_module = construct_hdl21_module(spice_netlist=spice_component_netlist)
+
+    h.netlist(
+        hdl21_module,
+        output_path,
+        fmt="spice",
+    )

piel/types/__init__.py

@@ -40,6 +40,7 @@
     SParameterCollection,
 )
 from .electronic import HVAMetricsType, LNAMetricsType, ElectronicCircuitComponent
+from .integration import CircuitComponent
 from .materials import (
     MaterialReferenceType,
     MaterialReferencesTypes,

piel/types/integration.py

@@ -0,0 +1,4 @@
+from .electronic import ElectronicCircuitComponent
+from .photonic import PhotonicCircuitComponent
+
+CircuitComponent = ElectronicCircuitComponent | PhotonicCircuitComponent