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antmicro/yosys-systemverilog#1743: Compensate for chipsalliance/Surelog#3670 #522

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hs-apotell
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chipsalliance/synlig#1743: Compensate for chipsalliance/Surelog#3670

UHDM model hierarchy changed to enforce vpiParent as weak reference.

@mglb
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mglb commented May 30, 2023

I did run the PR + chipsalliance/Surelog#3670 in yosys-systemverilog CI, many tests fail: https://github.com/antmicro/yosys-systemverilog/actions/runs/5121636527
I'll look into the Surelog/UHDM change soon to see what should be done in the plugin.

@hs-apotell
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I ran the CI pipeline in Surelog repository and the build passed. chipsalliance/Surelog#3681
Happy to assist in anyway possible.

The UHDM/Surelog change should have minimal impact outside the core implementation itself.

@hs-apotell
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@mglb Any update on this PR? Anything I can do to bump up the priority on this?

@mglb
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mglb commented Jun 2, 2023

@hs-apotell
Turns out the plugin doesn't work with Surelog's master, which is responsible for at least some issues from the yosys-systemverilog CI run linked above.
It would be best to wait until we catch up with the master branch - this work is already in progress.

@hs-apotell
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@hs-apotell Turns out the plugin doesn't work with Surelog's master, which is responsible for at least some issues from the yosys-systemverilog CI run linked above. It would be best to wait until we catch up with the master branch - this work is already in progress.

Appreciate the update. Let me know when you are ready to try out this change again and I can rebase the Surelog PR.

@mglb
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mglb commented Jun 7, 2023

@hs-apotell FYI: you can fork yosys-systemverilog, change submodule revisions/remotes to point to your changes, commit+push, and create a Draft PR. The CI will test it using code from revisions/forks configured on your branch.

Instructions how to change submodule can be found in the readme: https://github.com/antmicro/yosys-systemverilog#using-dedicated-branch

@hs-apotell
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Are the issues reported against Surelog master resolved?

UHDM model hierarchy changed to enforce vpiParent as weak reference.
@mglb
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mglb commented Jun 9, 2023

Every related issue reported against Surelog/UHDM has been fixed AFAIK.
With #528 merged, only one test in yosys-systemverilog fails with Surelog master.

@hs-apotell
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@mglb I forked the yosys-systemverilog repository and attempted a build it never gets executed. I have 3 builds waiting in the queue for over 10 hours.
https://github.com/Apotell/yosys-systemverilog/actions

Am I missing some required permissions for the self-hosted runners?

@pgielda
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pgielda commented Jun 10, 2023

Custom runners are "private" to an org. In principle the only way for them to run for external users is to open a PR to that org (so in this case to https://github.com/antmicro/yosys-systemverilog). You cannot use them "privately" (unless you set up exactly the same "private" infrastructure)

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3 participants