Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

generate xilinx pin constraints from .pkg file #55

Open
jameyhicks opened this issue Feb 13, 2015 · 5 comments
Open

generate xilinx pin constraints from .pkg file #55

jameyhicks opened this issue Feb 13, 2015 · 5 comments

Comments

@jameyhicks
Copy link
Member

e.g.,

Xilinx/Vivado/2014.4/data/parts/xilinx/zynq/zynq/xc7z020/clg400/clg400_7z020.pkg:

N2 | 148 PS_DDR_A0_502 N2
K2 | 149 PS_DDR_A1_502 K2
M3 | 150 PS_DDR_A2_502 M3
K3 | 151 PS_DDR_A3_502 K3

@jameyhicks
Copy link
Member Author

Larry found a reference to partgen, but that was part of the old tool suite. The Vivado migration guide points to some tcl commands that look interesting:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2012_3/ug911-vivado-migration.pdf

@jankcorn
Copy link
Member

How about using the file:
Xilinx/Vivado/2014.4/data/ip/xilinx/mig_7series_v2_3/data/fpga_tlib/zynq/7z/xc7z020clg400_pkg.xml
?
It looks much easier to parse (just standard XML)
I assume we are just trying to get the memory pins and this is part of the MemoryInterfaceGenerator support files.

@jameyhicks
Copy link
Member Author

It's true the format is very goofy.

I think if we can write a short tcl script that uses Xilinx's parser for their package files it would be better.

@jankcorn
Copy link
Member

deleted the package xdc files and all builds seem ok.
Turns out weren't needed after all.

@lstewart
Copy link
Contributor

I now think they are needed. Looking at, for example, examples/simple/zedboard/Impl/TopDown/pre_place_drc.rpt we see

NSTD-1#1 Critical Warning
Unspecified I/O Standard
130 out of 138 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may
cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extre
me cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O stand
ards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. T
o allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warn
ing} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command
to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: DDR_Addr[14:0
], DDR_BankAddr[2:0], DDR_DM[3:0], DDR_DQ[31:0], DDR_DQS_n[3:0], DDR_DQS_p[3:0], FIXED_IO_mio[53:0], DDR_CAS_n, DDR_CKE, DDR_CS_
n, DDR_Clk_n, DDR_Clk_p, DDR_DRSTB, DDR_ODT, DDR_RAS_n (the first 15 of 21 listed).
Related violations:

This probably has been set as a warning but it should be an error.
I am back looking for a way to generate the necessary xdc files

@lstewart lstewart reopened this Feb 18, 2015
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Projects
None yet
Development

No branches or pull requests

3 participants