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generate xilinx pin constraints from .pkg file #55
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Larry found a reference to partgen, but that was part of the old tool suite. The Vivado migration guide points to some tcl commands that look interesting: |
How about using the file: |
It's true the format is very goofy. I think if we can write a short tcl script that uses Xilinx's parser for their package files it would be better. |
deleted the package xdc files and all builds seem ok. |
I now think they are needed. Looking at, for example, examples/simple/zedboard/Impl/TopDown/pre_place_drc.rpt we see NSTD-1#1 Critical Warning This probably has been set as a warning but it should be an error. |
e.g.,
Xilinx/Vivado/2014.4/data/parts/xilinx/zynq/zynq/xc7z020/clg400/clg400_7z020.pkg:
N2 | 148 PS_DDR_A0_502 N2
K2 | 149 PS_DDR_A1_502 K2
M3 | 150 PS_DDR_A2_502 M3
K3 | 151 PS_DDR_A3_502 K3
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