Neg

codegen/templates/vec.rs.tera

@@ -3660,6 +3660,14 @@ impl Neg for {{ self_t }} {
         {% endif %}
     }
 }
+
+impl Neg for &{{ self_t }} {
+    type Output = {{ self_t }};
+    #[inline]
+    fn neg(self) -> {{ self_t }} {
+        (*self).neg()
+    }
+}
 {% endif %}
 
 {% if not is_float %}

src/f32/coresimd/vec3a.rs

@@ -1689,6 +1689,14 @@ impl Neg for Vec3A {
     }
 }
 
+impl Neg for &Vec3A {
+    type Output = Vec3A;
+    #[inline]
+    fn neg(self) -> Vec3A {
+        (*self).neg()
+    }
+}
+
 impl Index<usize> for Vec3A {
     type Output = f32;
     #[inline]

src/f32/coresimd/vec4.rs

@@ -1609,6 +1609,14 @@ impl Neg for Vec4 {
     }
 }
 
+impl Neg for &Vec4 {
+    type Output = Vec4;
+    #[inline]
+    fn neg(self) -> Vec4 {
+        (*self).neg()
+    }
+}
+
 impl Index<usize> for Vec4 {
     type Output = f32;
     #[inline]

src/f32/neon/vec3a.rs

@@ -1736,6 +1736,14 @@ impl Neg for Vec3A {
     }
 }
 
+impl Neg for &Vec3A {
+    type Output = Vec3A;
+    #[inline]
+    fn neg(self) -> Vec3A {
+        (*self).neg()
+    }
+}
+
 impl Index<usize> for Vec3A {
     type Output = f32;
     #[inline]

src/f32/neon/vec4.rs

@@ -1646,6 +1646,14 @@ impl Neg for Vec4 {
     }
 }
 
+impl Neg for &Vec4 {
+    type Output = Vec4;
+    #[inline]
+    fn neg(self) -> Vec4 {
+        (*self).neg()
+    }
+}
+
 impl Index<usize> for Vec4 {
     type Output = f32;
     #[inline]

src/f32/scalar/vec3a.rs

@@ -1813,6 +1813,14 @@ impl Neg for Vec3A {
     }
 }
 
+impl Neg for &Vec3A {
+    type Output = Vec3A;
+    #[inline]
+    fn neg(self) -> Vec3A {
+        (*self).neg()
+    }
+}
+
 impl Index<usize> for Vec3A {
     type Output = f32;
     #[inline]

src/f32/scalar/vec4.rs

@@ -1831,6 +1831,14 @@ impl Neg for Vec4 {
     }
 }
 
+impl Neg for &Vec4 {
+    type Output = Vec4;
+    #[inline]
+    fn neg(self) -> Vec4 {
+        (*self).neg()
+    }
+}
+
 impl Index<usize> for Vec4 {
     type Output = f32;
     #[inline]

src/f32/sse2/vec3a.rs

@@ -1744,6 +1744,14 @@ impl Neg for Vec3A {
     }
 }
 
+impl Neg for &Vec3A {
+    type Output = Vec3A;
+    #[inline]
+    fn neg(self) -> Vec3A {
+        (*self).neg()
+    }
+}
+
 impl Index<usize> for Vec3A {
     type Output = f32;
     #[inline]

src/f32/sse2/vec4.rs

@@ -1664,6 +1664,14 @@ impl Neg for Vec4 {
     }
 }
 
+impl Neg for &Vec4 {
+    type Output = Vec4;
+    #[inline]
+    fn neg(self) -> Vec4 {
+        (*self).neg()
+    }
+}
+
 impl Index<usize> for Vec4 {
     type Output = f32;
     #[inline]

src/f32/vec2.rs

@@ -1736,6 +1736,14 @@ impl Neg for Vec2 {
     }
 }
 
+impl Neg for &Vec2 {
+    type Output = Vec2;
+    #[inline]
+    fn neg(self) -> Vec2 {
+        (*self).neg()
+    }
+}
+
 impl Index<usize> for Vec2 {
     type Output = f32;
     #[inline]

src/f32/vec3.rs

@@ -1803,6 +1803,14 @@ impl Neg for Vec3 {
     }
 }
 
+impl Neg for &Vec3 {
+    type Output = Vec3;
+    #[inline]
+    fn neg(self) -> Vec3 {
+        (*self).neg()
+    }
+}
+
 impl Index<usize> for Vec3 {
     type Output = f32;
     #[inline]

src/f32/wasm32/vec3a.rs

@@ -1705,6 +1705,14 @@ impl Neg for Vec3A {
     }
 }
 
+impl Neg for &Vec3A {
+    type Output = Vec3A;
+    #[inline]
+    fn neg(self) -> Vec3A {
+        (*self).neg()
+    }
+}
+
 impl Index<usize> for Vec3A {
     type Output = f32;
     #[inline]

src/f32/wasm32/vec4.rs

@@ -1632,6 +1632,14 @@ impl Neg for Vec4 {
     }
 }
 
+impl Neg for &Vec4 {
+    type Output = Vec4;
+    #[inline]
+    fn neg(self) -> Vec4 {
+        (*self).neg()
+    }
+}
+
 impl Index<usize> for Vec4 {
     type Output = f32;
     #[inline]

src/f64/dvec2.rs

@@ -1736,6 +1736,14 @@ impl Neg for DVec2 {
     }
 }
 
+impl Neg for &DVec2 {
+    type Output = DVec2;
+    #[inline]
+    fn neg(self) -> DVec2 {
+        (*self).neg()
+    }
+}
+
 impl Index<usize> for DVec2 {
     type Output = f64;
     #[inline]

src/f64/dvec3.rs

@@ -1810,6 +1810,14 @@ impl Neg for DVec3 {
     }
 }
 
+impl Neg for &DVec3 {
+    type Output = DVec3;
+    #[inline]
+    fn neg(self) -> DVec3 {
+        (*self).neg()
+    }
+}
+
 impl Index<usize> for DVec3 {
     type Output = f64;
     #[inline]

src/f64/dvec4.rs

@@ -1820,6 +1820,14 @@ impl Neg for DVec4 {
     }
 }
 
+impl Neg for &DVec4 {
+    type Output = DVec4;
+    #[inline]
+    fn neg(self) -> DVec4 {
+        (*self).neg()
+    }
+}
+
 impl Index<usize> for DVec4 {
     type Output = f64;
     #[inline]

src/i16/i16vec2.rs

@@ -1354,6 +1354,14 @@ impl Neg for I16Vec2 {
     }
 }
 
+impl Neg for &I16Vec2 {
+    type Output = I16Vec2;
+    #[inline]
+    fn neg(self) -> I16Vec2 {
+        (*self).neg()
+    }
+}
+
 impl Not for I16Vec2 {
     type Output = Self;
     #[inline]

src/i16/i16vec3.rs

@@ -1429,6 +1429,14 @@ impl Neg for I16Vec3 {
     }
 }
 
+impl Neg for &I16Vec3 {
+    type Output = I16Vec3;
+    #[inline]
+    fn neg(self) -> I16Vec3 {
+        (*self).neg()
+    }
+}
+
 impl Not for I16Vec3 {
     type Output = Self;
     #[inline]

src/i16/i16vec4.rs

@@ -1495,6 +1495,14 @@ impl Neg for I16Vec4 {
     }
 }
 
+impl Neg for &I16Vec4 {
+    type Output = I16Vec4;
+    #[inline]
+    fn neg(self) -> I16Vec4 {
+        (*self).neg()
+    }
+}
+
 impl Not for I16Vec4 {
     type Output = Self;
     #[inline]

src/i32/ivec2.rs

@@ -1354,6 +1354,14 @@ impl Neg for IVec2 {
     }
 }
 
+impl Neg for &IVec2 {
+    type Output = IVec2;
+    #[inline]
+    fn neg(self) -> IVec2 {
+        (*self).neg()
+    }
+}
+
 impl Not for IVec2 {
     type Output = Self;
     #[inline]

src/i32/ivec3.rs

@@ -1429,6 +1429,14 @@ impl Neg for IVec3 {
     }
 }
 
+impl Neg for &IVec3 {
+    type Output = IVec3;
+    #[inline]
+    fn neg(self) -> IVec3 {
+        (*self).neg()
+    }
+}
+
 impl Not for IVec3 {
     type Output = Self;
     #[inline]

src/i32/ivec4.rs

@@ -1495,6 +1495,14 @@ impl Neg for IVec4 {
     }
 }
 
+impl Neg for &IVec4 {
+    type Output = IVec4;
+    #[inline]
+    fn neg(self) -> IVec4 {
+        (*self).neg()
+    }
+}
+
 impl Not for IVec4 {
     type Output = Self;
     #[inline]

src/i64/i64vec2.rs

@@ -1354,6 +1354,14 @@ impl Neg for I64Vec2 {
     }
 }
 
+impl Neg for &I64Vec2 {
+    type Output = I64Vec2;
+    #[inline]
+    fn neg(self) -> I64Vec2 {
+        (*self).neg()
+    }
+}
+
 impl Not for I64Vec2 {
     type Output = Self;
     #[inline]

src/i64/i64vec3.rs

@@ -1429,6 +1429,14 @@ impl Neg for I64Vec3 {
     }
 }
 
+impl Neg for &I64Vec3 {
+    type Output = I64Vec3;
+    #[inline]
+    fn neg(self) -> I64Vec3 {
+        (*self).neg()
+    }
+}
+
 impl Not for I64Vec3 {
     type Output = Self;
     #[inline]

src/i64/i64vec4.rs

@@ -1495,6 +1495,14 @@ impl Neg for I64Vec4 {
     }
 }
 
+impl Neg for &I64Vec4 {
+    type Output = I64Vec4;
+    #[inline]
+    fn neg(self) -> I64Vec4 {
+        (*self).neg()
+    }
+}
+
 impl Not for I64Vec4 {
     type Output = Self;
     #[inline]

tests/vec2.rs

@@ -662,6 +662,11 @@ macro_rules! impl_vec2_signed_tests {
             assert_eq!($new(0.0 as $t, -0.0 as $t), -$new(-0.0 as $t, 0.0 as $t));
         });
 
+        glam_test!(test_neg_propagation, {
+            let a = $new(1 as $t, 2 as $t);
+            assert_eq!(-a, -(&a));
+        });
+
         glam_test!(test_perp, {
             let v1 = $vec2::new(1 as $t, 2 as $t);
             let v2 = $vec2::new(1 as $t, 1 as $t);