[gateware] add bitstreams to repo

makefiles/in_chroot/install.sh

@@ -112,17 +112,21 @@ systemctl enable NetworkManager
 # build raw2dng
 cdmake software/misc-tools-utilities/raw2dng
 
-# download prebuilt fpga binaries & select the default binary
+# copy prebuilt fpga binaries & select the default binary
 # also convert the bitstreams to the format expected by the linux kernel
 mkdir -p /opt/bitstreams/
-BITSTREAMS="BETA/cmv_hdmi3_dual_60.bit BETA/cmv_hdmi3_dual_30.bit BETA/ICSP/icsp.bit check_pin10.bit check_pin20.bit"
-for bit in $BITSTREAMS; do
+for bit in peripherals/bitstreams/*.bit; do
     NAME=$(basename $bit)
-    (cd /opt/bitstreams && wget --no-verbose http://vserver.13thfloor.at/Stuff/AXIOM/$bit -O $NAME)
+    ln -sf $(pwd)/$bit /opt/bitstreams
     ./makefiles/in_chroot/to_raw_bitstream.py -f /opt/bitstreams/$NAME /opt/bitstreams/"$(basename ${NAME%.bit}).bin"
     ln -sf /opt/bitstreams/"${NAME%.bit}.bin" /lib/firmware
 done
-ln -sf /opt/bitstreams/cmv_hdmi3_dual_60.bin /lib/firmware/axiom-fpga-main.bin
+
+if [[ $DEVICE == 'micro' ]]; then
+  ln -sf /opt/bitstreams/micro_main.bin /lib/firmware/axiom_fpga_main.bin
+else
+  ln -sf /opt/bitstreams/cmv_hdmi3_dual_60.bin /lib/firmware/axiom_fpga_main.bin
+fi
 
 cp software/scripts/axiom_start.service /etc/systemd/system/
 if [[ $DEVICE == 'micro' ]]; then

peripherals/bitstreams/README.md

@@ -0,0 +1,13 @@
+# bitstreams
+Unfortunately building the gateware in a automated fashion is currently quite hard, as it needs vivado.
+Until nextpnr, yosys and ghdl are ready to build this gateware or we have switched to a nmigen based gateware, this folder will hold verious perbuilt bitstreams
+
+## contents
+### micro_main.bit
+This bitstream is for the AXIOM Micro r2, it reads out the AR0330 sensor and writes the sensor into a ringbuffer in the DDR3 RAM connected to the zynq. From there the data can sent away over ethernet.
+### cmv_hdmi3_dual_60.bit
+This bitstream is for the AXIOM Beta, it reads out the cmv12k sensor and outputs 1920x1080@60Hz HDMI on both plugin modules.
+### cmv_hdmi3_dual_30.bit
+This bitstream is for the AXIOM Beta, it reads out the cmv12k sensor and outputs 1920x1080@30Hz HDMI on both plugin modules.
+### icsp.bit, check_pin10.bit, check_pin20.bit
+These bitstreams are used for the initial bringup of a AXIOM Beta.

software/scripts/axiom_start.sh

@@ -6,7 +6,7 @@
 axiom_fclk_init.sh
 axiom_zynq_info.sh
 
-echo axiom-fpga-main.bin > /sys/class/fpga_manager/fpga0/firmware
+echo axiom_fpga_main.bin > /sys/class/fpga_manager/fpga0/firmware
 
 axiom_mem_reg -4 0xF8006210 0x00001
 axiom_mem_reg -4 0xF8006214 0x00001