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Merge pull request chipsalliance#444 from antmicro/bump-yosys
Update yosys
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Submodule yosys
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+4 −0 | CHANGELOG | |
+1 −1 | frontends/ast/genrtlil.cc | |
+17 −5 | frontends/ast/simplify.cc | |
+12 −3 | frontends/verilog/verilog_lexer.l | |
+4 −1 | frontends/verilog/verilog_parser.y | |
+1 −2 | tests/various/param_struct.ys | |
+43 −0 | tests/various/struct_access.sv | |
+5 −0 | tests/various/struct_access.ys | |
+25 −0 | tests/verilog/delay_time_scale.ys | |
+2 −3 | tests/verilog/struct_access.sv |
94 changes: 0 additions & 94 deletions
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yosys-patches/0003-Add-support-for-accessing-whole-struct.patch
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