docs: Update introduction chapter

antmicro · Nov 27, 2023 · 2a2d3c9 · 2a2d3c9
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diff --git a/docs/source/img/ipconnect.png b/docs/source/img/ipconnect.png
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diff --git a/docs/source/introduction.md b/docs/source/introduction.md
@@ -1,22 +1,16 @@
 # Introduction
 
-Topwrap is a generator for HDL wrappers and top modules.
+Topwrap is a tool for generating HDL wrappers for simple blocks as well as digital systems and can be used for creating complex SoCs from single blocks contained in wrappers.
 
-Wrappers are used to standardize names of ports that belong to an interfaces (e.g. UART, AXI etc.)
+
+## Wrappers
+These wrappers standardize names of ports that belong to an interfaces (e.g. UART, AXI etc.)
 
 ```{image} img/wrapper.png
 ```
-
+## Top module
 Top modules connect IPs and/or Wrappers by either ports\` names or interfaces\` names to ease connecting multi-wire interfaces without the need to connect each wire separately.
 
 ```{image} img/ipconnect.png
 ```
 
-## Amaranth
-
-Topwrap uses Amaranth to generate HDLs. It's a toolbox for building complex digital hardware.
-See [Amaranth Github](https://github.com/amaranth-lang/amaranth) for more information.
-
-## FuseSoC
-
-FuseSoC is used as build abstraction tool. It automates Vivado project generation and runs Vivado pipelines to generate bitstream and program FPGAs. It can be installed using `pip`. For more information visit [FuseSoC Github](https://github.com/olofk/fusesoc).