Support for 4.90C and 4.91C

MGZ/source/common.h

@@ -1073,4 +1073,56 @@
 #define OFFSET_1_IDPS_489C         0x80000000003E2E30ULL
 #define OFFSET_2_IDPS_489C         0x8000000000474AF4ULL
 
+#define TOC_490C                   0x800000000034FBA0ULL
+#define SYSCALL_TABLE_490C         0x8000000000363BE0ULL
+#define HV_START_OFFSET_490C       0x370F28
+#define HTAB_OFFSET_490C           0x2DD70C
+#define HTAB_PATCH1_490C           0x05D5EC
+#define HTAB_PATCH2_490C           0x05E024
+#define HTAB_PATCH3_490C           0x05E4EC
+#define MMAP_OFFSET1_490C          0x2DCF54
+#define MMAP_OFFSET2_490C          0x2DD284
+#define SPE_OFFSET_490C            0x2F9EB8
+#define OFFSET_FIX_490C            0x056588
+#define OFFSET_2_FIX_490C          0x05A6E0
+#define OFFSET_FIX_2B17_490C       0x2275EC
+#define OFFSET_FIX_LIC_490C        0x05622C
+#define OFFSET_FIX_3C_490C         0x267148
+#define OPEN_HOOK_490C             0x800000000029762CULL
+#define BASE_ADDR_490C             0x80000000002D8AE0ULL
+#define LV2MOUNTADDR_490C          0x8000000000479FC0ULL
+#define LV2MOUNTADDR_ESIZE_490C    0x118
+#define LV2MOUNTADDR_CSIZE_490C    0x108
+#define FW_DATE_OFFSET_490C        0x80000000002FCB58ULL
+#define FW_DATE_1_490C             0x323032322F31322FULL
+#define FW_DATE_2_490C             0x31322031353A3131ULL
+#define OFFSET_1_IDPS_490C         0x80000000003E2E30ULL
+#define OFFSET_2_IDPS_490C         0x8000000000474AF4ULL
+
+#define TOC_491C                   0x800000000034FBB0ULL
+#define SYSCALL_TABLE_491C         0x8000000000363BE0ULL
+#define HV_START_OFFSET_491C       0x370F28
+#define HTAB_OFFSET_491C           0x2DD70C
+#define HTAB_PATCH1_491C           0x05D5F0
+#define HTAB_PATCH2_491C           0x05E028
+#define HTAB_PATCH3_491C           0x05E4F0
+#define MMAP_OFFSET1_491C          0x2DCF54
+#define MMAP_OFFSET2_491C          0x2DD284
+#define SPE_OFFSET_491C            0x2F9EB8
+#define OFFSET_FIX_491C            0x05658C
+#define OFFSET_2_FIX_491C          0x05A6E4
+#define OFFSET_FIX_2B17_491C       0x2275F4
+#define OFFSET_FIX_LIC_491C        0x056230
+#define OFFSET_FIX_3C_491C         0x267150
+#define OPEN_HOOK_491C             0x8000000000297638ULL
+#define BASE_ADDR_491C             0x80000000002D8AF0ULL
+#define LV2MOUNTADDR_491C          0x8000000000479FC0ULL
+#define LV2MOUNTADDR_ESIZE_491C    0x118
+#define LV2MOUNTADDR_CSIZE_491C    0x108
+#define FW_DATE_OFFSET_491C        0x80000000002FCB68ULL
+#define FW_DATE_1_491C             0x323032332F31322FULL
+#define FW_DATE_2_491C             0x30372031333A3432ULL
+#define OFFSET_1_IDPS_491C         0x80000000003E2E30ULL
+#define OFFSET_2_IDPS_491C         0x8000000000474AF4ULL
+
 #endif /* __COMMON_H__ */

MGZ/source/data.h

@@ -249,5 +249,16 @@
 #include "mamba_489C_lz_bin.h"
 #include "mamba_loader_489C_bin.h"
 
+#include "erk_dumper_490C_bin.h"
+#include "payload_sky_490C_bin.h"
+#include "umount_490C_bin.h"
+#include "mamba_490C_lz_bin.h"
+#include "mamba_loader_490C_bin.h"
+
+#include "erk_dumper_491C_bin.h"
+#include "payload_sky_491C_bin.h"
+#include "umount_491C_bin.h"
+#include "mamba_491C_lz_bin.h"
+#include "mamba_loader_491C_bin.h"
 
 #endif /* __DATA_H__ */

MGZ/source/fw.c

@@ -1682,6 +1682,88 @@ u8 init_fw()
 		ERK_DUMPER_SIZE = erk_dumper_489C_bin_size;
 		ERK_DUMPER = (u64 *) erk_dumper_489C_bin;
 
+	} else
+	if(( lv2peek(FW_DATE_OFFSET_490C    )==FW_DATE_1_490C) &&
+	   ( lv2peek(FW_DATE_OFFSET_490C + 8)==FW_DATE_2_490C) )
+	{
+
+		firmware = 0x490C;
+
+		OFFSET_2_FIX = OFFSET_2_FIX_490C;
+		LV2MOUNTADDR_ESIZE = LV2MOUNTADDR_ESIZE_490C;
+		LV2MOUNTADDR_CSIZE = LV2MOUNTADDR_CSIZE_490C;
+		OFFSET_FIX = OFFSET_FIX_490C;
+		HV_START_OFFSET = HV_START_OFFSET_490C;
+		OFFSET_FIX_2B17 = OFFSET_FIX_2B17_490C;
+		OFFSET_FIX_LIC = OFFSET_FIX_LIC_490C;
+		OFFSET_FIX_3C = OFFSET_FIX_3C_490C;
+		TOC = TOC_490C;
+		SYSCALL_TABLE = SYSCALL_TABLE_490C;
+		HTAB_OFFSET = HTAB_OFFSET_490C;
+		HTAB_PATCH1 = HTAB_PATCH1_490C;
+		HTAB_PATCH2 = HTAB_PATCH2_490C;
+		HTAB_PATCH3 = HTAB_PATCH3_490C;
+		MMAP_OFFSET1 = MMAP_OFFSET1_490C;
+		MMAP_OFFSET2 = MMAP_OFFSET2_490C;
+		SPE_OFFSET = SPE_OFFSET_490C;
+		LV2MOUNTADDR = LV2MOUNTADDR_490C;
+		OPEN_HOOK = OPEN_HOOK_490C;
+		BASE_ADDR = BASE_ADDR_490C;
+		OFFSET_1_IDPS = OFFSET_1_IDPS_490C;
+		OFFSET_2_IDPS = OFFSET_2_IDPS_490C;
+
+		PAYLOAD_SKY_SIZE = payload_sky_490C_bin_size;
+		PAYLOAD_SKY = (u64) payload_sky_490C_bin;
+		UMOUNT_SIZE = umount_490C_bin_size;
+		UMOUNT = (u64) umount_490C_bin;
+		MAMBA_SIZE = mamba_490C_lz_bin_size;
+		MAMBA = (u64) mamba_490C_lz_bin;
+		MAMBA_LOADER_SIZE = mamba_loader_490C_bin_size;
+		MAMBA_LOADER = (u64 *) mamba_loader_490C_bin;
+		ERK_DUMPER_SIZE = erk_dumper_490C_bin_size;
+		ERK_DUMPER = (u64 *) erk_dumper_490C_bin;
+
+	} else
+	if(( lv2peek(FW_DATE_OFFSET_491C    )==FW_DATE_1_491C) &&
+	   ( lv2peek(FW_DATE_OFFSET_491C + 8)==FW_DATE_2_491C) )
+	{
+
+		firmware = 0x491C;
+
+		OFFSET_2_FIX = OFFSET_2_FIX_491C;
+		LV2MOUNTADDR_ESIZE = LV2MOUNTADDR_ESIZE_491C;
+		LV2MOUNTADDR_CSIZE = LV2MOUNTADDR_CSIZE_491C;
+		OFFSET_FIX = OFFSET_FIX_491C;
+		HV_START_OFFSET = HV_START_OFFSET_491C;
+		OFFSET_FIX_2B17 = OFFSET_FIX_2B17_491C;
+		OFFSET_FIX_LIC = OFFSET_FIX_LIC_491C;
+		OFFSET_FIX_3C = OFFSET_FIX_3C_491C;
+		TOC = TOC_491C;
+		SYSCALL_TABLE = SYSCALL_TABLE_491C;
+		HTAB_OFFSET = HTAB_OFFSET_491C;
+		HTAB_PATCH1 = HTAB_PATCH1_491C;
+		HTAB_PATCH2 = HTAB_PATCH2_491C;
+		HTAB_PATCH3 = HTAB_PATCH3_491C;
+		MMAP_OFFSET1 = MMAP_OFFSET1_491C;
+		MMAP_OFFSET2 = MMAP_OFFSET2_491C;
+		SPE_OFFSET = SPE_OFFSET_491C;
+		LV2MOUNTADDR = LV2MOUNTADDR_491C;
+		OPEN_HOOK = OPEN_HOOK_491C;
+		BASE_ADDR = BASE_ADDR_491C;
+		OFFSET_1_IDPS = OFFSET_1_IDPS_491C;
+		OFFSET_2_IDPS = OFFSET_2_IDPS_491C;
+
+		PAYLOAD_SKY_SIZE = payload_sky_491C_bin_size;
+		PAYLOAD_SKY = (u64) payload_sky_491C_bin;
+		UMOUNT_SIZE = umount_491C_bin_size;
+		UMOUNT = (u64) umount_491C_bin;
+		MAMBA_SIZE = mamba_491C_lz_bin_size;
+		MAMBA = (u64) mamba_491C_lz_bin;
+		MAMBA_LOADER_SIZE = mamba_loader_491C_bin_size;
+		MAMBA_LOADER = (u64 *) mamba_loader_491C_bin;
+		ERK_DUMPER_SIZE = erk_dumper_491C_bin_size;
+		ERK_DUMPER = (u64 *) erk_dumper_491C_bin;
+
 	} else {return FAILED;}
 
 	NEW_POKE_SYSCALL_ADDR = lv2peek( lv2peek(SYSCALL_TABLE + NEW_POKE_SYSCALL*8) ) + 0ULL;

MGZ/source/fw_unk.c

@@ -5,7 +5,7 @@
 #include "extern.h"
 
 // todo : include this with offsetfinder
-#define LAST_FW(x)   (x##_488C)
+#define LAST_FW(x)   (x##_491C)
 
 u8 compare(u8 ignore, char *mem, char *flag, u32 size)
 {

MGZ/source/ps2crc.h

@@ -49,6 +49,8 @@
 #define CRC32HWEMU_487C        0xB80DB089
 #define CRC32HWEMU_488C        0x179695A6
 #define CRC32HWEMU_489C        0xE96E0840
+#define CRC32HWEMU_490C        0x18F28950
+#define CRC32HWEMU_491C        0x2808351A
 
 #define CRC32GXEMU_421C        0xE031E18E
 #define CRC32GXEMU_421D        0x513B3FD1
@@ -96,6 +98,8 @@
 #define CRC32GXEMU_487C        0x9C1D118B
 #define CRC32GXEMU_488C        0x9C1D118B
 #define CRC32GXEMU_489C        0x9C1D118B
+#define CRC32GXEMU_490C        0x36A7D81A
+#define CRC32GXEMU_491C        0x36A7D81A
 
 #define CRC32NETEMU_421C        0x6CCC9066
 #define CRC32NETEMU_421D        0x4EBC5CFC
@@ -143,5 +147,7 @@
 #define CRC32NETEMU_487C        0x93E0EB0B
 #define CRC32NETEMU_488C        0x93E0EB0B
 #define CRC32NETEMU_489C        0x93E0EB0B
+#define CRC32NETEMU_490C        0x75C6886D
+#define CRC32NETEMU_491C        0x75C6886D
 
 #endif /* __PS2CRC_H__ */

MGZ/source/ps2data.h

@@ -279,5 +279,16 @@
 #include "ps2gxemu_stage2_489C_bin.h"
 #include "ps2netemu_stage2_489C_bin.h"
 
+#include "ps2hwemu_stage1_490C_bin.h"
+#include "ps2hwemu_stage2_490C_bin.h"
+#include "ps2gxemu_stage1_490C_bin.h"
+#include "ps2gxemu_stage2_490C_bin.h"
+#include "ps2netemu_stage2_490C_bin.h"
+
+#include "ps2hwemu_stage1_491C_bin.h"
+#include "ps2hwemu_stage2_491C_bin.h"
+#include "ps2gxemu_stage1_491C_bin.h"
+#include "ps2gxemu_stage2_491C_bin.h"
+#include "ps2netemu_stage2_491C_bin.h"
 
 #endif /* __PS2DATA_H__ */

MGZ/source/ps2vers.c

@@ -282,6 +282,18 @@ u8 get_hwemu(u32 crc, u8 **stage1, u32 *stage1_size, u8 **stage2, u32 *stage2_si
 		*stage1 = (uint8_t *) ps2hwemu_stage1_489C_bin;
 		*stage2_size = (uint32_t) ps2hwemu_stage2_489C_bin_size;
 		*stage2 = (uint8_t *) ps2hwemu_stage2_489C_bin;
+	} else
+	if(crc == CRC32HWEMU_490C) {
+		*stage1_size = (uint32_t) ps2hwemu_stage1_490C_bin_size;
+		*stage1 = (uint8_t *) ps2hwemu_stage1_490C_bin;
+		*stage2_size = (uint32_t) ps2hwemu_stage2_490C_bin_size;
+		*stage2 = (uint8_t *) ps2hwemu_stage2_490C_bin;
+	} else
+	if(crc == CRC32HWEMU_491C) {
+		*stage1_size = (uint32_t) ps2hwemu_stage1_491C_bin_size;
+		*stage1 = (uint8_t *) ps2hwemu_stage1_491C_bin;
+		*stage2_size = (uint32_t) ps2hwemu_stage2_491C_bin_size;
+		*stage2 = (uint8_t *) ps2hwemu_stage2_491C_bin;
 	} else  return FAILED;
 
 	return SUCCESS;
@@ -565,6 +577,18 @@ u8 get_gxemu(u32 crc, u8 **stage1, u32 *stage1_size, u8 **stage2, u32 *stage2_si
 		*stage1 = (uint8_t *) ps2gxemu_stage1_489C_bin;
 		*stage2_size = (uint32_t) ps2gxemu_stage2_489C_bin_size;
 		*stage2 = (uint8_t *) ps2gxemu_stage2_489C_bin;
+	} else
+	if(crc == CRC32GXEMU_490C) {
+		*stage1_size = (uint32_t) ps2gxemu_stage1_490C_bin_size;
+		*stage1 = (uint8_t *) ps2gxemu_stage1_490C_bin;
+		*stage2_size = (uint32_t) ps2gxemu_stage2_490C_bin_size;
+		*stage2 = (uint8_t *) ps2gxemu_stage2_490C_bin;
+	} else
+	if(crc == CRC32GXEMU_491C) {
+		*stage1_size = (uint32_t) ps2gxemu_stage1_491C_bin_size;
+		*stage1 = (uint8_t *) ps2gxemu_stage1_491C_bin;
+		*stage2_size = (uint32_t) ps2gxemu_stage2_491C_bin_size;
+		*stage2 = (uint8_t *) ps2gxemu_stage2_491C_bin;
 	} else  return FAILED;
 
 	return SUCCESS;
@@ -757,6 +781,14 @@ u8 get_netemu(u32 crc, u8 **stage2, u32 *stage2_size)
 	if(crc == CRC32NETEMU_489C) {
 		*stage2_size = (uint32_t) ps2netemu_stage2_489C_bin_size;
 		*stage2 = (uint8_t *) ps2netemu_stage2_489C_bin;
+	} else
+	if(crc == CRC32NETEMU_490C) {
+		*stage2_size = (uint32_t) ps2netemu_stage2_490C_bin_size;
+		*stage2 = (uint8_t *) ps2netemu_stage2_490C_bin;
+	} else
+	if(crc == CRC32NETEMU_491C) {
+		*stage2_size = (uint32_t) ps2netemu_stage2_491C_bin_size;
+		*stage2 = (uint8_t *) ps2netemu_stage2_491C_bin;
 	} else  return FAILED;
 
 	return SUCCESS;

payloads/FIRMWARES

@@ -1,3 +1,3 @@
-PAYLOADS     :=421C 421D 430C 430D 431C 440C 441C 441D 446C 446D 450C 450D 453C 453D 455C 455D 460C 465C 465D 470C 470D 475C 475D 476C 476D 478C 478D 480C 480D 481C 481D 482C 482D 483C 484C 484D 485C 486C 487C 488C 489C 
+PAYLOADS     :=421C 421D 430C 430D 431C 440C 441C 441D 446C 446D 450C 450D 453C 453D 455C 455D 460C 465C 465D 470C 470D 475C 475D 476C 476D 478C 478D 480C 480D 481C 481D 482C 482D 483C 484C 484D 485C 486C 487C 488C 489C 490C 491C
 
-PS2_PAYLOADS := 421C 421D 425C 425D 430C 430D 431C 431D 440C 440D 441C 441D 446C 446D 450C 450D 453C 453D 455C 455D 460C 460D 465C 465D 466C 470C 470D 475C 475D 476C 476D 478C 478D 480C 480D 481C 481D 482C 483C 484C 484D 485C 486C 487C 488C 489C 
+PS2_PAYLOADS := 421C 421D 425C 425D 430C 430D 431C 431D 440C 440D 441C 441D 446C 446D 450C 450D 453C 453D 455C 455D 460C 460D 465C 465D 466C 470C 470D 475C 475D 476C 476D 478C 478D 480C 480D 481C 481D 482C 483C 484C 484D 485C 486C 487C 488C 489C 490C 491C