Extension and Verification

##Unit Tests Generation##

MIAOW includes a suite of unit tests that exercise all of the implemented instructions. These include not only the instructions and register values but also instruction traces generated by multi2sim, an emulator used to generate reference values for instruction, register, and memory values. The instruction traces are currently generated using a patched version of multi2sim, the source of which we make available here. We are working to merge our changes upstream so that in the future one does not need our patches. The input values (Scalar and Vector register contents) for the unit tests are randomly generated. The infrastructure for unit test development is included in $TOP_DIR/src/sw/siagen.

The following are the steps for creating unit tests for newly added instructions:

1. cd $TOP_DIR/src/sw/siagen

2. Open siagen.cpp. There are multiple subroutines for each set of instructions. For example, to add the scalar instruction "waitcnt" which is of type SOPP and has an opcode 0X0C, add that instruction to the sopp_ops vector. There are corresponding vectors for each type of instruction.

For further support or questions regarding this, please contact: [email protected] or [email protected]

3. Once the modifications are complete, do make to generate the executable ./siagen.

4. The usage of siagen is explained below:

   Usage:
   ./siagen -i <instruction_mix> -r <registers> -m <data_memory> -c <instr_count> -t <thread count> -w <workgroup count> -n <number of tests> -u <unit test>

   Options: (All required)
   i - Instruction mix represented as ratio <scalar_alu_instr>:<vector_alu_instr>:<scalar_mem_instr>:<vector_mem_instr>
   r - Absolute number of scalar and vector registers <scalar_reg>:<vector_reg> m - Data memory required c - Total instruction count t - Number of threads per workgroup w - Number of workgroups n - Number of tests to generate u - Create unit tests (i, c, w, n are overridden)

   Example: ./siagen -i 10:10:10:10 -r 12:12 -m 10000 -c 10 -t 10 -w 1 -n 10 -u 1 The above command creates unit tests for all the instructions, each unit test having the following files:

   • unit_test_config.txt - The configuration file consists of information about number of threads, LDS size and the input values to 12 scalar/vector registers.
   • unit_test_data.mem - The data memory dump with data values for the LDS size of 10000 bytes.
   • unit_test_instr.mem - The instruction memory dump.

   NOTE: During unit test generation, parameters i, c, w, and n are overridden - meaning their effect is not considered.

5. The unit tests are generated in the same folder. Copy over them to $TOP_DIR/src/sw/miaow_unit_tests to generate reference (golden) traces using multi2sim.

Generating Multi2Sim Traces

Multi2Sim is the reference simulator used to generate the golden traces for unit tests and the benchmarks. MIAOW requires a modified version of multi2sim that can be acquired here. The three folders that are unzipped need to be placed within the src/sw directory.

In the multi2sim-4.*/bin/ directory, make the m2s file executable by running chmod +x m2s.

In the src/sw/common/ directory, make the trace_parser.pl file executable by running chmod +x trace_parser.pl.

Go to the folder $TOP_DIR/src/sw/miaow_unit_tests and run the run script by typing ./run. Type ./run -h for more running options specifying the specific tests to generate traces for, and the version of Multi2Sim to use.

The Golden Traces will be generated and placed within the /src/sw/miaow_unit_tests/test_*/kernel_*/ directory for each test.

config.txt contains the test configuration.

• The first line is `(# of kernels);(# of threads per kernel)`
  

• The second line is `(wavegroup ID);(wavefront ID);(# of wavefronts);(# of threads);(# of vector registers);(# scalar registers);(max # clock cycles);(contents of vector registers);(contents of scalar registers)`
  

• The contents of the registers are delimited by `;`, and each vector register is further separated into 32-bit scalar components delimited by `,`. 
  

• `data_*.mem` contains the data memory contents to initialize. 
  

• `instr_*.mem` contains the instruction memory contents to initialize. 
  

• `test_*` contains the Golden Trace. It includes: 
  

  • Assembly language program, in order of execution
    

  • Instruction memory location and HEX machine code for each assembly instruction
    

  • Register content changes, for instructions that change the register contents
    

##Workload Development

MIAOW also has a series of more intensive benchmarks that exercise the compute unit more extensively. These include AMD APP OpenCL kernels located at $TOP_DIR/src/sw/benchmarks and also Rodinia Suite located at $TOP_DIR/src/sw/rodinia. MIAOW supports all of the AMD APP kernels and five of the Rodinia OpenCL kernels. Users of this tool can start developing the support for more kernels.