Author: Shyam Razesh
Acknowledgments: SoC design Program by Mr. Kunal Ghosh , VLSI System Design
This repository contains all the information studied and created during the Digital VLSI SoC Design and Planning workshop. It is primarily foucused on a complete RTL2GDS flow using the open-soucre flow named OpenLANE. PICORV32A RISC-V core design is used for the purpose.
RTL to GDSII Flow refers to the all the steps involved in converting a logical Register Transfer Level(RTL) Design to a fabrication ready GDSII format. GDSII is a database file format which is an industry standard for data exchange of IC layout artwork. The RTL to GSDII flow consists of following steps:
- RTL Synthesis
- Static Timing Analysis(STA)
- Design for Testability(DFT)
- Floorplanning
- Placement
- Clock Tree Synthesis(CTS)
- Routing
- GDSII Streaming
All the steps are further discussed in details in the repository.
Google and SkyWater Technology Foundry in collaboration have released a completely open-source Process Design Kit(PDK) in May, 2020. The current release target to a SKY130 (i.e. 130 nm) process node is available as SkyWater Open Source PDK. The PDK provides Physical VLSI Designer with a wide range of flexibility in design choices. All the designs and simulations listed in this repository are carried out using the same SkyWater Open Source PDK.
| Name of Tool | Application / Usage |
|---|---|
| Yosys | Synthesis of RTL Design |
| ABC | Mapping of Netlist |
| OpenSTA | Static Timing Analysis |
| OpenROAD | Floorplanning, Placement, CTS, Optimization, Routing |
| TritonRoute | Detailed Routing |
| Magic VLSI | Layout Tool |
| NGSPICE | SPICE Extraction and Simulation |
| SPEF_EXTRACTOR | Generation of SPEF file from DEF file |
The above list of tools shows that, many different tools are required for various tasks in Physical VLSI Design. Each tool in itself have number of system requirements and require various supporting tools to be installed. Installing each tool one-by-one seems in-efficient. This is made easy by some custom scripts that setup the required tools and environment for them in just a few easy steps. To install all the required tools, one can refer to the below mentioned repositories:
- VSDFlow - Installs Yosys, Magic, OpenTimer, OpenSTA and some other supporting tools
- OpenLANE Build Scripts - Install all required OpenROAD and some supporting tools
It is the process of designing an ASIC chip that uses digital logic components, as opposed to analog.
-
Synthesis:
- RTL Analysis: Conduct RTL analysis to ensure the correctness and completeness of the RTL design. Identify and address any issues related to combinational loops, clock domain crossings (CDC), and other potential synthesis issues.
- Logic Synthesis: Translate the RTL design into a gate-level netlist using logic synthesis tools. Optimize the netlist for area, power, and timing based on specified constraints.
- Technology Mapping: Map the synthesized logic gates to cells from the target technology library. This step involves selecting the appropriate cells and optimizing the mapping for timing and area.
-
Floor Planning with Power Planning:
- Floor Planning: Define the physical layout of the chip by allocating space for different functional blocks, such as logic cores, memory blocks, I/O pads, and power grid structures. Consider factors such as chip size, aspect ratio, and placement of critical components.
- Macro floor planning: This includes defining of the dimensions, pin locations, row etc.
- Power Planning: Design the power distribution network (PDN) to ensure stable and reliable power delivery to all parts of the chip. Place power pads and create power rails, power straps, and decoupling capacitors to minimize voltage drop and noise.
-
Placement:Using a post-synthesis netlist and floor-planning/physical design limitations, arranging the standard cells on the chip to create a physical layout.
- Global Placement: Perform global placement to assign initial positions to cells on the chip while considering factors such as timing, congestion, and wirelength.
- Detailed Placement: Refine the placement by optimizing cell positions to minimize wirelength, reduce congestion, and meet timing constraints. Ensure proper placement of critical paths and avoid hotspots.
-
Clock Tree Synthesis (CTS):
- Clock Tree Synthesis: Design and optimize the clock distribution network to ensure consistent and reliable clock signals across the chip. Generate a balanced clock tree that minimizes clock skew and meets timing requirements for all clock domains.Involves providing clock signals to all the sequential elements in the design to obtain minimum skew usually in the form of a tree(H, X, pi tree, Fish Bone).
-
Routing:
- Global Routing: Create the initial routing topology by determining the paths for signal wires, clock lines, and power/ground connections. Resolve conflicts and congestion to achieve a feasible routing solution.
- Detailed Routing: Perform detailed routing to physically implement the routing paths generated during global routing. Optimize wire lengths, minimize parasitic effects, and ensure signal integrity. Use techniques such as via insertion, wire spreading, and metal layer assignment. Includes making wires to connect the various cells to create a physical layout.
-
Signoff:
-
Design Rule Checking (DRC): Run design rule checks to verify that the layout adheres to the manufacturing rules and constraints specified by the foundry.
-
Layout vs. Schematic (LVS) Verification: Perform layout vs. schematic checks to ensure the layout matches the intended circuit functionality.
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Timing Analysis: Conduct static timing analysis (STA) to verify timing constraints, including setup time, hold time, and clock skew, and ensure that timing requirements are met across the chip.
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Power Analysis: Analyze power consumption and distribution to ensure that power constraints are satisfied and that the PDN is robust.
-
Physical Verification: Perform full-chip physical verification to ensure the layout is free from manufacturing defects and meets reliability criteria.
Basic Linux Commands cd: opens the particular folder ls: lists the content of the folder pwd: shows the present working directory mkdir: to make a new directory command --help: shows the complete use of that command clear: clears the terminal screen
Working on sky130A(pdk) which contains libs.tech which has respective files on tools such as magic, netgen etc., and libs.ref which has files related to the specific technology.
cd Desktop cd work/tools cd openlane_working_dir cd openlane
After getting into the directory, enter the commands
docker pwd ls -ltrTo open the openlane in interactive mode,
You may run the interactively by using the
-interactiveoption:./flow.tcl -interactive
To prepare the openlane,
package require openlane 0.9 prep - design picorv32a
-
To run the Synthesis the cmd i.e,
run_synthesis
Before running, we saw that the result folder was empty. But now, after running the synthesis, we can see that all the mapping has been done by ABC. And in the report, we can see when the actual synthesis has been done. and the actual statistics synthesis report is shown below, which is the same as what we have seen before.
Particularly we are interested in finding the Flop ratio. This can be calculated by using the formula:
Flop Ratio = No. of D FlipfLops/Total No. of cells
=1613/14876
=0.10842
Percentage of D FF's = 10.842%
Chip area for the module = 147712.9184
The Synthesis Report are found in the directory
~/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/01-04_19-21/reports/synthesis/1-yosys_4.stat.rptThe synthesis Results are found in the directory
~/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/01-04_19-21/results/synthesis/picorv32a.synthesis.v-
Run 'picorv32a' design floorplan using OpenLANE flow and generate necessary outputs.
-
Calculate the die area in microns from the values in floorplan def.
-
Load generated floorplan def in magic tool and explore the floorplan.
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Run 'picorv32a' design congestion aware placement using OpenLANE flow and generate necessary outputs.
-
Load generated placement def in magic tool and explore the placement.
- All section 2 logs, reports and results can be found in following run folder:
The LAB gives the complete flow of the Floorplanning and the placement process After the Synthesis process, type the command for running the Floor planning
The configuration files are inside the location
/Desktop/work/tools/openlane_working_dir/openlane/configurations/README.mdBefore run the floorplanning, we required some switches for the floorplanning. these we can get from the configuration from openlane.
Here we can see that the core utilization ratio is 50% (bydefault) and aspect ratio is 1 (bydefault). similarly other information is also given. But it is not neccessory to take these values. we need to change these value as per the given requirments also.
Here FP_PDN files are set the power distribution network. These switches are set in the floorplane stage bydefault in OpenLANE.
Here, (FP_IO MODE) 1, 0 means pin positioning is random but it is on equal distance.
In the OpenLANE lower priority is given to system default (floorplanning.tcl), the next priority is given to config.tcl and then priority is given to PDK varient.tcl (sky130A_sky130_fd_sc_hd_congig.tcl).
In the run folder, we can see the connfig.tcl file. this file contains all the configuration that are taken by the flow. if we open the config.tcl file, then we can see that which are the parameters are accepted in the current flow.
In this particular location from the floorplan.def file, we can able to see the area of the chip
1000 unit distance = 1 Micron
Distance in micron = value
----------
1000
Die width in micron = 660685
---------
1000
Die height in micron = 671405
---------
1000
Area of die in micron = 660.685*671.405 Square micron
Locate to this directory
~/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/01-04_19-21/results/floorplanTo see the actual layout after the flow, we have to open the magic file by adding the command magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.floorplan.def &
- Floorplan def in Magic
- The side rows,the Decap cells are arranged at the border of the side rows.
-
Horizontal metal layer
-
Vertical metal layer
- Subcells
-
Standard cells
-
To watch how Placementplane looks, we have to go in the results.
-
These switches are set in the Placementplane stage bydefault in OpenLANE.
-
Before run the Placement, we required some switches for the Placement. these we can get from the configuration from openlane.
To run the Placement, the command is
run_placement
The Magic file to see actual view of standerd cells placement.And the actual view in the magic file is given below.
Commands to load placement def in magic
magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.placement.def &
-
If we zooom into this, we can find the buffers, gates, flip flops in this.
-
Via
-
Vertical metal layer., metal 4
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Horizontal metal layer i.e., metal 5
1.Clone custom inverter standard cell design from github repository: Standard cell design and characterization using OpenLANE flow.
2.Load the custom inverter layout in magic and explore.
3.Spice extraction of inverter in magic.
4.Editing the spice model file for analysis through simulation.
5.Post-layout ngspice simulations.
6.Find problem in the DRC section of the old magic tech file for the skywater process and fix them.
- Topmost cell in window picorv32a
Every Design is represented by an equivalent cell design. All the standard cell designs are available in the Cell Library. A fully custom cell design that meets all rules can be added to the library. To begin with, a CMOS Inverter is designed in Magic Layout Tool and analysis is carried out using NGSPICE tool.
Go to this directory to git clone the files
/Desktop/work/tools/openlane_working_dir/openlane
Git clone the files from GitHub to your local pc
git clone https://github.com/nickson-jose/vsdstdcelldesign.git
open another terminal and go to the location
/home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic
copy the sky130A.tech file from this location to the git cloned location.
Now, we can see that this file is copied in the vsdstdcelldesign folder.
Now initialize magic
magic -T sky130A.tech sky130_inv.mag &
-In sky130, every color is showing the different layer. here the first layer is for local interconnect shown by blue_purple color, then second layer is metal 1 which is shown by light purple color, and the metal 2 is shown by pink color. N-well is shown by solide das line. green is N-diffusion region. and red is for polysilicon gate. similarly the brown color is for P-diffusion.
- Inverter layout
- nmos
we will check for the output terminal also.(by double pressing "S" to select the entire thing at output Y).
so, we can see that "Y" is attached to locali in cell def sky130_inv.
we can check the source of the PMOS is connected to the ground or not. and similarly we can check it for NMOS also.
-
Connection between source and VDD in Pmos
-
Connection between source and Ground in Nmos
Now open the tkcon window and type the commands for extracting the files. Bute before that see lets see its location
`pwd`
To extract the file from here, we have to write the command in tckon window and the comand is extract all
we will use this .ext file to create the spice file to be use with our ngspice tool. for that we have apply the command ext2spice cthresh 0 rthresh 0,
this will not create anything new.
now again we have to type ext2spice command in tckon window.
so, now we are checking the location and at there spice file has been created.
let's see what is inside the spice file by "vim sky130_inv.spice".
Now we have to include the PMOS and NMOS lib files. it is inside the libs folder in the vsdstdcellsdesign folder.
let's see inside PMOS lib file.
Measuring unit distance in layout grid
run the spice file in ngspice
ngspice sky130_inv.spice
To plot the graph between Voltage and time type the command in ngspice
plot y vs time a
after running this file we get output of ngspice like this,
-
Transient response output V = 3.3v
80% of V is 2.64v
20% of V is 0.65v
-80% value
-80% value
Fall transition time = Time taken for output to fall from 20% - Time taken for output to fall from 80%= 4.09511 ns - 4.05263 ns = 0.04248 ns
-20% value
Rise transition time = Time taken for output to rise from 80% - Time taken for output to rise from 20%
= 2.4577 ns - 2.182 ns
= 0.06377 ns
-20% value
Rise propagation delay = Time taken for output to rise to 50% - Time taken for input to fall to 50%
= 2.2113 ns - 2.15 ns
= 0.0613 ns
Fall propagation delay = Time taken for output to fall to 50% - Time taken for input to rise to 50%
= 4.07806 ns - 4.05056 ns
= 0.0275 ns
- Fix up small DRC errors and verify the design is ready to be inserted into our flow.
- Save the finalized layout with custom name and open it.
- Generate lef from the layout.
- Copy the newly generated lef and associated required lib files to 'picorv32a' design 'src' directory.
- Edit 'config.tcl' to change lib file and add the new extra lef into the openlane flow.
- Run openlane flow synthesis with newly inserted custom inverter cell.
- Remove/reduce the newly introduced violations with the introduction of custom inverter cell by modifying design parameters.
- Once synthesis has accepted our custom inverter we can now run floorplan and placement and verify the cell is accepted in PnR flow.
- Do Post-Synthesis timing analysis with OpenSTA tool.
- Make timing ECO fixes to remove all violations.
- Replace the old netlist with the new netlist generated after timing ECO fix and implement the floorplan, placement and cts.
- Post-CTS OpenROAD timing analysis.
- Explore post-CTS OpenROAD timing analysis by removing 'sky130_fd_sc_hd__clkbuf_1' cell from clock buffer list variable 'CTS_CLK_BUFFER_LIST'.
-Fix up small DRC errors and verify the design is ready to be inserted into our flow. Conditions to be verified before moving forward with custom designed cell layout:
Condition 1: The input and output ports of the standard cell should lie on the intersection of the vertical and horizontal tracks.
Condition 2: Width of the standard cell should be odd multiples of the horizontal track pitch.
Condition 3: Height of the standard cell should be even multiples of the vertical track pitch.
Commands to open the custom inverter layout
# Change directory to vsdstdcelldesign
cd Desktop/work/tools/openlane_working_dir/openlane/vsdstdcelldesign
# Command to open custom inverter layout in magic
magic -T sky130A.tech sky130_inv.mag &Screenshot of tracks.info of sky130_fd_sc_hd
Commands for tkcon window to set grid as tracks of locali layer
# Get syntax for grid command
help grid
# Set grid values accordingly
grid 0.46um 0.34um 0.23um 0.17umScreenshot of commands run
Save the finalized layout with custom name and open it.
Command for tkcon window to save the layout with custom name
# Command to save as
save sky130_vsdinv.mag
Command to open the newly saved layout
# Command to open custom inverter layout in magic
magic -T sky130A.tech sky130_vsdinv.mag &Screenshot of newly saved layout
Generate lef from the layout.
Command for tkcon window to write lef
# lef command
lef writeScreenshot of command run
Screenshot of newly created lef file
Copy the newly generated lef and associated required lib files to 'picorv32a' design 'src' directory. Commands to copy necessary files to 'picorv32a' design 'src' directory
# Copy lef file
cp sky130_vsdinv.lef ~/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/src/
# List and check whether it's copied
ls ~/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/src/
# Copy lib files
cp libs/sky130_fd_sc_hd__* ~/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/src/
# List and check whether it's copied
ls ~/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/src/Screenshot of commands run
Run openlane flow synthesis with newly inserted custom inverter cell.
Commands to invoke the OpenLANE flow include new lef and perform synthesis
# Change directory to openlane flow directory
cd Desktop/work/tools/openlane_working_dir/openlane
# alias docker='docker run -it -v $(pwd):/openLANE_flow -v $PDK_ROOT:$PDK_ROOT -e PDK_ROOT=$PDK_ROOT -u $(id -u $USER):$(id -g $USER) efabless/openlane:v0.21'
# Since we have aliased the long command to 'docker' we can invoke the OpenLANE flow docker sub-system by just running this command
docker
# Now that we have entered the OpenLANE flow contained docker sub-system we can invoke the OpenLANE flow in the Interactive mode using the following command
./flow.tcl -interactive
# Now that OpenLANE flow is open we have to input the required packages for proper functionality of the OpenLANE flow
package require openlane 0.9
# Now the OpenLANE flow is ready to run any design and initially we have to prep the design creating some necessary files and directories for running a specific design which in our case is 'picorv32a'
prep -design picorv32a
# Adiitional commands to include newly added lef to openlane flow
set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
add_lefs -src $lefs
# Now that the design is prepped and ready, we can run synthesis using following command
run_synthesisScreenshots of commands run
-Remove/reduce the newly introduced violations with the introduction of custom inverter cell by modifying design parameters.
Noting down current design values generated before modifying parameters to improve timing
Commands to view and change parameters to improve timing and run synthesis
# Now once again we have to prep design so as to update variables
prep -design picorv32a -tag 24-03_10-03 -overwrite
# Addiitional commands to include newly added lef to openlane flow merged.lef
set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
add_lefs -src $lefs
# Command to display current value of variable SYNTH_STRATEGY
echo $::env(SYNTH_STRATEGY)
# Command to set new value for SYNTH_STRATEGY
set ::env(SYNTH_STRATEGY) "DELAY 3"
# Command to display current value of variable SYNTH_BUFFERING to check whether it's enabled
echo $::env(SYNTH_BUFFERING)
# Command to display current value of variable SYNTH_SIZING
echo $::env(SYNTH_SIZING)
# Command to set new value for SYNTH_SIZING
set ::env(SYNTH_SIZING) 1
# Command to display current value of variable SYNTH_DRIVING_CELL to check whether it's the proper cell or not
echo $::env(SYNTH_DRIVING_CELL)
# Now that the design is prepped and ready, we can run synthesis using following command
run_synthesisScreenshot of merged.lef in tmp directory with our custom inverter as macro
-Once synthesis has accepted our custom inverter we can now run floorplan and placement and verify the cell is accepted in PnR flow.
Now that our custom inverter is properly accepted in synthesis we can now run floorplan using following command
# Now we can run floorplan
run_floorplanScreenshots of command run
Since we are facing unexpected un-explainable error while using run_floorplan command, we can instead use the following set of commands available based on information from Desktop/work/tools/openlane_working_dir/openlane/scripts/tcl_commands/floorplan.tcl and also based on Floorplan Commands section in Desktop/work/tools/openlane_working_dir/openlane/docs/source/OpenLANE_commands.md
# Follwing commands are alltogather sourced in "run_floorplan" command
init_floorplan
place_io
tap_decap_orScreenshots of commands run
Now that floorplan is done we can do placement using following command
# Now we are ready to run placement
run_placementScreenshots of command run
Commands to load placement def in magic in another terminal
# Change directory to path containing generated placement def
cd Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/24-03_10-03/results/placement/
# Command to load the placement def in magic tool
magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read
picorv32a.placement.def &Screenshot of placement def in magic
Screenshot of custom inverter inserted in placement def with proper abutment
Command for tkcon window to view internal layers of cells
# Command to view internal connectivity layers
expandThe abutment of power pins with other cell from library clearly visible
Before run the further stage, lets see cts we can get from the configuration from openlane and also cts.tcl file.
- Do Post-Synthesis timing analysis with OpenSTA tool.
Since we are having 0 wns after improved timing run we are going to do timing analysis on initial run of synthesis which has lots of violations and no parameters were added to improve timing
Commands to invoke the OpenLANE flow include new lef and perform synthesis
# Change directory to openlane flow directory
cd Desktop/work/tools/openlane_working_dir/openlane
# alias docker='docker run -it -v $(pwd):/openLANE_flow -v $PDK_ROOT:$PDK_ROOT -e PDK_ROOT=$PDK_ROOT -u $(id -u $USER):$(id -g $USER) efabless/openlane:v0.21'
# Since we have aliased the long command to 'docker' we can invoke the OpenLANE flow docker sub-system by just running this command
docker
# Now that we have entered the OpenLANE flow contained docker sub-system we can invoke the OpenLANE flow in the Interactive mode using the following command
./flow.tcl -interactive
# Now that OpenLANE flow is open we have to input the required packages for proper functionality of the OpenLANE flow
package require openlane 0.9
# Now the OpenLANE flow is ready to run any design and initially we have to prep the design creating some necessary files and directories for running a specific design which in our case is 'picorv32a'
prep -design picorv32a
# Adiitional commands to include newly added lef to openlane flow
set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
add_lefs -src $lefs
# Command to set new value for SYNTH_SIZING
set ::env(SYNTH_SIZING) 1
# Now that the design is prepped and ready, we can run synthesis using following command
run_synthesisCommands run final screenshot
Newly created pre_sta.conf for STA analysis in openlane directory
Newly created my_base.sdc for STA analysis in openlane/designs/picorv32a/src directory based on the file openlane/scripts/base.sdc
Commands to run STA in another terminal
# Change directory to openlane
cd Desktop/work/tools/openlane_working_dir/openlane
# Command to invoke OpenSTA tool with script
sta pre_sta.confScreenshots of commands run
Since more fanout is causing more delay we can add parameter to reduce fanout and do synthesis again
Commands to include new lef and perform synthesis
# Now the OpenLANE flow is ready to run any design and initially we have to prep the design creating some necessary files and directories for running a specific design which in our case is 'picorv32a'
prep -design picorv32a -tag 01-04_19-21 -overwrite
# Adiitional commands to include newly added lef to openlane flow
set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
add_lefs -src $lefs
# Command to set new value for SYNTH_SIZING
set ::env(SYNTH_SIZING) 1
# Command to set new value for SYNTH_MAX_FANOUT
set ::env(SYNTH_MAX_FANOUT) 4
# Command to display current value of variable SYNTH_DRIVING_CELL to check whether it's the proper cell or not
echo $::env(SYNTH_DRIVING_CELL)
# Now that the design is prepped and ready, we can run synthesis using following command
run_synthesisCommands run final screenshot
Commands to run STA in another terminal
# Change directory to openlane
cd Desktop/work/tools/openlane_working_dir/openlane
# Command to invoke OpenSTA tool with script
sta pre_sta.confScreenshots of commands run
- Make timing ECO fixes to remove all violations.
OR gate of drive strength 2 is driving 4 fanouts
Commands to perform analysis and optimize timing by replacing with OR gate of drive strength 2, but turns out to reduce of slack is less due to less driving strength
# Reports all the connections to a net
report_net -connections _11675_
# Replacing cell
replace_cell _14514_ sky130_fd_sc_hd__or3_2
# Generating custom timing report
report_checks -fields {net cap slew input_pins} -digits 4Result - slack reduced
OR gate of drive strength 2 is driving 4 fanouts
Commands to perform analysis and optimize timing by replacing with OR gate of drive strength 4
# Reports all the connections to a net
report_net -connections _11672_
# Checking command syntax
help replace_cell
# Replacing cell
replace_cell _14510_ sky130_fd_sc_hd__or3_4
# Generating custom timing report
report_checks -fields {net cap slew input_pins} -digits 4Result - slack reduced
OR gate of drive strength 2 driving OA gate has more delay
Commands to perform analysis and optimize timing by replacing with OR gate of drive strength 4
# Reports all the connections to a net
report_net -connections _11643_
# Replacing cell
replace_cell _14481_ sky130_fd_sc_hd__or4_4
# Generating custom timing report
report_checks -fields {net cap slew input_pins} -digits 4Result - slack reduced
OR gate of drive strength 2 driving OA gate has more delay
Commands to perform analysis and optimize timing by replacing with OR gate of drive strength 4
# Reports all the connections to a net
report_net -connections _11668_
# Replacing cell
replace_cell _14506_ sky130_fd_sc_hd__or4_4
# Generating custom timing report
report_checks -fields {net cap slew input_pins} -digits 4Result - slack reduced
Commands to verify instance _14506_ is replaced with sky130_fd_sc_hd__or4_4
# Generating custom timing report
report_checks -from _29043_ -to _30440_ -through _14506_Screenshot of replaced instance
We started ECO fixes at wns -23.9000 and now we stand at wns -22.6173 we reduced around 1.2827 ns of violation
- Replace the old netlist with the new netlist generated after timing ECO fix and implement the floorplan, placement, and cts.
Now to insert this updated netlist to the PnR flow, we can use write_verilog and overwrite the synthesis netlist but before that, we are going to make a copy of the old netlist
Commands to make a copy of netlist
# Change from home directory to synthesis results directory
cd Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/25-03_18-52/results/synthesis/
# List contents of the directory
ls
# Copy and rename the netlist
cp picorv32a.synthesis.v picorv32a.synthesis_old.v
# List contents of the directory
lsScreenshot of commands run
Commands to write verilog
# Check syntax
help write_verilog
# Overwriting current synthesis netlist
write_verilog /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/25-03_18-52/results/synthesis/picorv32a.synthesis.v
# Exit from OpenSTA since timing analysis is done
exitScreenshot of commands run
Verified that the netlist is overwritten by checking that instance 14506 is replaced with sky130_fd_sc_hd__or4_4
Since we confirmed that netlist is replaced and will be loaded in PnR but since we want to follow up on the earlier 0 violation design we are continuing with the clean design to further stages
Commands load the design and run necessary stages
# Now once again we have to prep design so as to update variables
prep -design picorv32a -tag 24-03_10-03 -overwrite
# Addiitional commands to include newly added lef to openlane flow merged.lef
set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
add_lefs -src $lefs
# Command to set new value for SYNTH_STRATEGY
set ::env(SYNTH_STRATEGY) "DELAY 3"
# Command to set new value for SYNTH_SIZING
set ::env(SYNTH_SIZING) 1
# Now that the design is prepped and ready, we can run synthesis using following command
run_synthesis
# Follwing commands are alltogather sourced in "run_floorplan" command
init_floorplan
place_io
tap_decap_or
# Now we are ready to run placement
run_placement
# Incase getting error
unset ::env(LIB_CTS)
# With placement done we are now ready to run CTS
run_ctsScreenshots of commands run
- Explore post-CTS OpenROAD timing analysis by removing ' sky130_fd_sc_hd__clkbuf_1 ' cell from clock buffer list variable 'CTS_CLK_BUFFER_LIST'.
Commands to be run in OpenLANE flow to do OpenROAD timing analysis after changing CTS_CLK_BUFFER_LIST
# Checking current value of 'CTS_CLK_BUFFER_LIST'
echo $::env(CTS_CLK_BUFFER_LIST)
# Removing 'sky130_fd_sc_hd__clkbuf_1' from the list
set ::env(CTS_CLK_BUFFER_LIST) [lreplace $::env(CTS_CLK_BUFFER_LIST) 0 0]
# Checking current value of 'CTS_CLK_BUFFER_LIST'
echo $::env(CTS_CLK_BUFFER_LIST)
# Checking current value of 'CURRENT_DEF'
echo $::env(CURRENT_DEF)
# Setting def as placement def
set ::env(CURRENT_DEF) /openLANE_flow/designs/picorv32a/runs/24-03_10-03/results/placement/picorv32a.placement.def
# Run CTS again
run_cts
# Checking current value of 'CTS_CLK_BUFFER_LIST'
echo $::env(CTS_CLK_BUFFER_LIST)
# Command to run OpenROAD tool
openroad
# Reading lef file
read_lef /openLANE_flow/designs/picorv32a/runs/24-03_10-03/tmp/merged.lef
# Reading def file
read_def /openLANE_flow/designs/picorv32a/runs/24-03_10-03/results/cts/picorv32a.cts.def
# Creating an OpenROAD database to work with
write_db pico_cts1.db
# Loading the created database in OpenROAD
read_db pico_cts.db
# Read netlist post CTS
read_verilog /openLANE_flow/designs/picorv32a/runs/24-03_10-03/results/synthesis/picorv32a.synthesis_cts.v
# Read library for design
read_liberty $::env(LIB_SYNTH_COMPLETE)
# Link design and library
link_design picorv32a
# Read in the custom sdc we created
read_sdc /openLANE_flow/designs/picorv32a/src/my_base.sdc
# Setting all cloks as propagated clocks
set_propagated_clock [all_clocks]
# Generating custom timing report
report_checks -path_delay min_max -fields {slew trans net cap input_pins} -format full_clock_expanded -digits 4
# Report hold skew
report_clock_skew -hold
# Report setup skew
report_clock_skew -setup
# Exit to OpenLANE flow
exit
# Checking current value of 'CTS_CLK_BUFFER_LIST'
echo $::env(CTS_CLK_BUFFER_LIST)
# Inserting 'sky130_fd_sc_hd__clkbuf_1' to first index of list
set ::env(CTS_CLK_BUFFER_LIST) [linsert $::env(CTS_CLK_BUFFER_LIST) 0 sky130_fd_sc_hd__clkbuf_1]
# Checking current value of 'CTS_CLK_BUFFER_LIST'
echo $::env(CTS_CLK_BUFFER_LIST)Screenshots of commands run and timing report generated
- Post-CTS OpenROAD timing analysis. Commands to be run in OpenLANE flow to do OpenROAD timing analysis with integrated OpenSTA in OpenROAD
# Command to run OpenROAD tool
openroad
# Reading lef file
read_lef /openLANE_flow/designs/picorv32a/runs/24-03_10-03/tmp/merged.lef
# Reading def file
read_def /openLANE_flow/designs/picorv32a/runs/24-03_10-03/results/cts/picorv32a.cts.def
# Creating an OpenROAD database to work with
write_db pico_cts.db
# Loading the created database in OpenROAD
read_db pico_cts.db
# Read netlist post CTS
read_verilog /openLANE_flow/designs/picorv32a/runs/24-03_10-03/results/synthesis/picorv32a.synthesis_cts.v
# Read library for design
read_liberty $::env(LIB_SYNTH_COMPLETE)
# Link design and library
link_design picorv32a
# Read in the custom sdc we created
read_sdc /openLANE_flow/designs/picorv32a/src/my_base.sdc
# Setting all cloks as propagated clocks
set_propagated_clock [all_clocks]
# Check syntax of 'report_checks' command
help report_checks
# Generating custom timing report
report_checks -path_delay min_max -fields {slew trans net cap input_pins} -format full_clock_expanded -digits 4
# Exit to OpenLANE flow
exitScreenshots of commands run and timing report generated
- Perform generation of Power Distribution Network (PDN) and explore the PDN layout.
- Perfrom detailed routing using TritonRoute.
- Post-Route parasitic extraction using SPEF extractor.
- Post-Route OpenSTA timing analysis with the extracted parasitics of the route.
- Perform generation of Power Distribution Network (PDN) and explore the PDN layout.
Commands to perform all necessary stages up until now
# Change directory to openlane flow directory
cd Desktop/work/tools/openlane_working_dir/openlane
# alias docker='docker run -it -v $(pwd):/openLANE_flow -v $PDK_ROOT:$PDK_ROOT -e PDK_ROOT=$PDK_ROOT -u $(id -u $USER):$(id -g $USER) efabless/openlane:v0.21'
# Since we have aliased the long command to 'docker' we can invoke the OpenLANE flow docker sub-system by just running this command
docker
# Now that we have entered the OpenLANE flow contained docker sub-system we can invoke the OpenLANE flow in the Interactive mode using the following command
./flow.tcl -interactive
# Now that OpenLANE flow is open we have to input the required packages for the proper functionality of the OpenLANE flow
package require openlane 0.9
# Now the OpenLANE flow is ready to run any design and initially we have to prep the design creating some necessary files and directories for running a specific design which in our case is 'picorv32a'
prep -design picorv32a
# Addiitional commands to include newly added lef to openlane flow merged.lef
set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
add_lefs -src $lefs
# Command to set new value for SYNTH_STRATEGY
set ::env(SYNTH_STRATEGY) "DELAY 3"
# Command to set new value for SYNTH_SIZING
set ::env(SYNTH_SIZING) 1
# Now that the design is prepped and ready, we can run synthesis using following command
run_synthesis
# Following commands are alltogather sourced in "run_floorplan" command
init_floorplan
place_io
tap_decap_or
# Now we are ready to run placement
run_placement
# Incase getting error
unset ::env(LIB_CTS)
# With placement done we are now ready to run CTS
run_cts
# Now that CTS is done we can do power distribution network
gen_pdnScreenshots of power distribution network run
Commands to load PDN def in magic in another terminal
# Change directory to path containing generated PDN def
cd Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/26-03_08-45/tmp/floorplan/
# Command to load the PDN def in magic tool
magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read 14-pdn.def &Screenshots of PDN def
- Basics of global and detail routing and configure TritonRoute
The final step of physical design is Routing.
The usage of the
defcommand in the image above is to indicate that the latest completed step was the generation of PDN.
The resulting file 17-pdn.def contains the information from cts.def as well as the power distribution network.
If one wants to learn about the various switches available for routing, they can refer to the README.md file located in the configuration folder of the OpenLANE directory.
-
By executing specific commands, we can determine the type of global and detailed routing that will be performed. In case we want to change the routing type, we can use the
setcommand followed by the parameter names mentioned in the routing section of the README.md file. -
Perform detailed routing using TritonRoute and explore the routed layout. Command to perform routing
```bash # Check value of 'CURRENT_DEF' echo $::env(CURRENT_DEF) # Check value of 'ROUTING_STRATEGY' echo $::env(ROUTING_STRATEGY) # Command for detailed route using TritonRoute run_routing ```
Screenshots of routing run
Commands to load routed def in magic in another terminal
# Change directory to path containing routed def
cd Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/26-03_08-45/results/routing/
# Command to load the routed def in magic tool
magic -T /home/vsduser/Desktop/work/tools/openlane_working_dir/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.lef def read picorv32a.def &
Screenshots of routed def
Screenshot of fast route guide present in openlane/designs/picorv32a/runs/01-04_19-21/tmp/routing directory
- Post-Route parasitic extraction using SPEF extractor.
Commands for SPEF extraction using external tool
# Change directory
cd Desktop/work/tools/SPEF_EXTRACTOR
# Command extract spef
python3 main.py /home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/26-03_08-45/tmp/merged.lef
/home/vsduser/Desktop/work/tools/openlane_working_dir/openlane/designs/picorv32a/runs/26-03_08-45/results/routing/picorv32a.def
- RISC-V : https://riscv.org/
- VLSI System Design: https://www.vlsisystemdesign.com/
- OpenLANE: https://github.com/The-OpenROAD-Project/OpenLane
- Skywater 130 PDK: https://github.com/google/skywater-pdk
- Open_PDKS: http://www.opencircuitdesign.com/open_pdks/
- Dgital VLSI Soc Design and planning: https://vsdsquadron.vlsisystemdesign.com/digital-vlsi-soc-design-and-planning/
- Kunal Ghosh, Co-founder, VSD Corp. Pvt. Ltd.
- Nickson Jose