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[bsp][renesas] initial commit for ra6e2-fpb
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XYX12306 authored and Rbb666 committed Oct 30, 2024
1 parent 91fe5ec commit 09bb076
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1 change: 1 addition & 0 deletions .github/workflows/bsp_buildings.yml
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Expand Up @@ -235,6 +235,7 @@ jobs:
- "renesas/ra6m4-iot"
- "renesas/ra6m3-ek"
- "renesas/ra6m3-hmi-board"
- "renesas/ra6e2-fpb"
- "renesas/ra4m2-eco"
- "renesas/ra2l1-cpk"
- "renesas/ra8m1-ek"
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24 changes: 24 additions & 0 deletions bsp/renesas/libraries/HAL_Drivers/config/drv_config.h
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Expand Up @@ -155,6 +155,30 @@ extern "C"

#endif /* SOC_SERIES_R9A07G0 */

#if defined(SOC_SERIES_R7FA6E2)
#include "ra6e2/uart_config.h"

#ifdef BSP_USING_ADC
#include "ra6e2/adc_config.h"
#endif

#ifdef BSP_USING_DAC
#include "ra6e2/dac_config.h"
#endif

#ifdef BSP_USING_PWM
#include "ra6e2/pwm_config.h"
#endif

#ifdef BSP_USING_TIM
#include "ra6e2/timer_config.h"
#endif

#ifdef BSP_USING_CAN
#include "ra6e2/can_config.h"
#endif
#endif /* SOC_SERIES_R7FA6E2 */

#ifdef __cplusplus
}
#endif
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42 changes: 42 additions & 0 deletions bsp/renesas/libraries/HAL_Drivers/config/ra6e2/adc_config.h
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@@ -0,0 +1,42 @@
/*
* Copyright (c) 2006-2024, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-19 Mr.Tiger first version
*/

#ifndef __ADC_CONFIG_H__
#define __ADC_CONFIG_H__

#include <rtthread.h>
#include <rtdevice.h>
#include "hal_data.h"
#ifdef __cplusplus
extern "C" {
#endif

#if defined(BSP_USING_ADC0) || defined(BSP_USING_ADC1)

struct rt_adc_dev
{
struct rt_adc_ops ops;
struct rt_adc_device adc_device;
};

struct ra_adc_map
{
const char *device_name;
const adc_cfg_t *g_cfg;
const adc_ctrl_t *g_ctrl;
const adc_channel_cfg_t *g_channel_cfg;
};
#endif
#endif

#ifdef __cplusplus
}
#endif

48 changes: 48 additions & 0 deletions bsp/renesas/libraries/HAL_Drivers/config/ra6e2/can_config.h
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@@ -0,0 +1,48 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-10-29 mazhiyuan first version
*/

#ifndef __CAN_CONFIG_H__
#define __CAN_CONFIG_H__

#include <rtthread.h>
#include "hal_data.h"

#ifdef __cplusplus
extern "C" {
#endif

#if defined(BSP_USING_CAN0)
#ifndef CAN0_CONFIG
#define CAN0_CONFIG \
{ \
.name = "can0", \
.num_of_mailboxs = CAN_NO_OF_MAILBOXES_g_can0, \
.p_api_ctrl = &g_can0_ctrl, \
.p_cfg = &g_can0_cfg, \
}
#endif /* CAN0_CONFIG */
#endif /* BSP_USING_CAN0 */

#if defined(BSP_USING_CAN1)
#ifndef CAN1_CONFIG
#define CAN1_CONFIG \
{ \
.name = "can1", \
.num_of_mailboxs = CAN_NO_OF_MAILBOXES_g_can1, \
.p_api_ctrl = &g_can1_ctrl, \
.p_cfg = &g_can1_cfg, \
}
#endif /* CAN1_CONFIG */
#endif /* BSP_USING_CAN1 */

#ifdef __cplusplus
}
#endif
#endif
41 changes: 41 additions & 0 deletions bsp/renesas/libraries/HAL_Drivers/config/ra6e2/dac_config.h
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@@ -0,0 +1,41 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-08-19 Mr.Tiger first version
*/

#ifndef __DAC_CONFIG_H__
#define __DAC_CONFIG_H__

#include <rtthread.h>
#include <rtdevice.h>
#include "hal_data.h"
#ifdef __cplusplus
extern "C" {
#endif

#ifdef BSP_USING_DAC
struct ra_dac_map
{
char name;
const struct st_dac_cfg *g_cfg;
const struct st_dac_instance_ctrl *g_ctrl;
};

struct ra_dac_dev
{
rt_dac_device_t ra_dac_device_t;
struct ra_dac_map *ra_dac_map_dev;
};
#endif

#endif

#ifdef __cplusplus
}
#endif

31 changes: 31 additions & 0 deletions bsp/renesas/libraries/HAL_Drivers/config/ra6e2/lcd_config.h
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@@ -0,0 +1,31 @@
/*
* Copyright (c) 2006-2024, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2024-03-01 Rbb666 the first version
*/
#ifndef __LCD_CONFIG_H_
#define __LCD_CONFIG_H_

typedef enum
{
ROTATION_ZERO = 0,
ROTATION_090 = 90,
ROTATION_180 = 180,
ROTATION_270 = 270,
} bsp_rotation;

#define LCD_WIDTH DISPLAY_HSIZE_INPUT0
#define LCD_HEIGHT DISPLAY_VSIZE_INPUT0
#define LCD_BITS_PER_PIXEL DISPLAY_BITS_PER_PIXEL_INPUT1
#define LCD_PIXEL_FORMAT RTGRAPHIC_PIXEL_FORMAT_RGB565
#define LCD_BUF_SIZE (LCD_WIDTH * LCD_HEIGHT * LCD_BITS_PER_PIXEL / 8)

#define ENABLE_DOUBLE_BUFFER (0)

#define LCD_BL_PIN BSP_IO_PORT_01_PIN_00

#endif
68 changes: 68 additions & 0 deletions bsp/renesas/libraries/HAL_Drivers/config/ra6e2/pwm_config.h
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/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-10-26 KevinXu first version
*/
#ifndef __PWM_CONFIG_H__
#define __PWM_CONFIG_H__

#include <rtthread.h>
#include <drv_config.h>
#include "hal_data.h"

#ifdef __cplusplus
extern "C" {
#endif

enum
{
#ifdef BSP_USING_PWM0
BSP_PWM0_INDEX,
#endif
#ifdef BSP_USING_PWM1
BSP_PWM1_INDEX,
#endif
#ifdef BSP_USING_PWM2
BSP_PWM2_INDEX,
#endif
#ifdef BSP_USING_PWM3
BSP_PWM3_INDEX,
#endif
#ifdef BSP_USING_PWM4
BSP_PWM4_INDEX,
#endif
#ifdef BSP_USING_PWM5
BSP_PWM5_INDEX,
#endif
#ifdef BSP_USING_PWM6
BSP_PWM6_INDEX,
#endif
#ifdef BSP_USING_PWM7
BSP_PWM7_INDEX,
#endif
#ifdef BSP_USING_PWM8
BSP_PWM8_INDEX,
#endif
#ifdef BSP_USING_PWM9
BSP_PWM9_INDEX,
#endif
BSP_PWMS_NUM
};

#define PWM_DRV_INITIALIZER(num) \
{ \
.name = "pwm"#num , \
.g_cfg = &g_timer##num##_cfg, \
.g_ctrl = &g_timer##num##_ctrl, \
.g_timer = &g_timer##num, \
}

#ifdef __cplusplus
}
#endif

#endif /* __PWM_CONFIG_H__ */
67 changes: 67 additions & 0 deletions bsp/renesas/libraries/HAL_Drivers/config/ra6e2/timer_config.h
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@@ -0,0 +1,67 @@
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2023-09-04 Rbb666 first version
*/

#ifndef __TIMER_CONFIG_H__
#define __TIMER_CONFIG_H__

#include <rtthread.h>
#include <drv_config.h>
#include "hal_data.h"

#ifdef __cplusplus
extern "C"
{
#endif

#define PLCKD_PRESCALER_MAX_SELECT 7

/* RA6M3: Frequency ratio: PCLKA:PCLKD = 1:N (N = 1/2/4/8/16/32/64) */
#define PLCKD_PRESCALER_120M (BSP_FEATURE_GPT_ODC_FREQ_MAX)
#define PLCKD_PRESCALER_60M (BSP_FEATURE_GPT_ODC_FREQ_MAX / 2)
#define PLCKD_PRESCALER_30M (BSP_FEATURE_GPT_ODC_FREQ_MAX / 4)
#define PLCKD_PRESCALER_15M (BSP_FEATURE_GPT_ODC_FREQ_MAX / 8)
#define PLCKD_PRESCALER_7_5M (BSP_FEATURE_GPT_ODC_FREQ_MAX / 16)
#define PLCKD_PRESCALER_3_75M (BSP_FEATURE_GPT_ODC_FREQ_MAX / 32)
#define PLCKD_PRESCALER_1_875M (BSP_FEATURE_GPT_ODC_FREQ_MAX / 64)

#ifndef TMR_DEV_INFO_CONFIG
#define TMR_DEV_INFO_CONFIG \
{ \
.maxfreq = 120000000, \
.minfreq = 1875000, \
.maxcnt = 0XFFFFFFFF, \
.cntmode = HWTIMER_CNTMODE_UP, \
}
#endif /* TIM_DEV_INFO_CONFIG */

enum
{
#ifdef BSP_USING_TIM0
BSP_TIMER0_INDEX,
#endif
#ifdef BSP_USING_TIM1
BSP_TIMER1_INDEX,
#endif
BSP_TIMERS_NUM
};

#define TIMER_DRV_INITIALIZER(num) \
{ \
.name = "timer" #num, \
.g_cfg = &g_timer##num##_cfg, \
.g_ctrl = &g_timer##num##_ctrl, \
.g_timer = &g_timer##num, \
}

#ifdef __cplusplus
}
#endif

#endif /* __TIMER_CONFIG_H__ */
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